参数资料
型号: 93LC46T-I/MS
元件分类: PROM
英文描述: 64 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封装: PLASTIC, MSOP-8
文件页数: 2/20页
文件大小: 510K
代理商: 93LC46T-I/MS
93XX46, 93XX46A/B
DS21749A-page 10
2002 Microchip Technology Inc.
2.9
WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the falling edge of the CS, except on ‘C’
devices where the rising edge of CLK before the last
data bit initiates the write cycle. Clocking of the CLK pin
is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL
instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL).
FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-11: WRAL TIMING FOR 93C DEVICES
CS
CLK
DI
DO
HIGH-Z
1
0
01
X
X
Dx
D0
HIGH-Z
BUSY
READY
T
WL
Ensured at Vcc = 4.5V to +5.5V.
T
CSL
T
SV
T
CZ
CS
CLK
DI
DO
HIGH-Z
1
0
01
X
X
Dx
D0
HIGH-Z
BUSY
READY
T
WL
T
CSL
T
SV
T
CZ
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