参数资料
型号: 93LC56AP
厂商: Microchip Technology Inc.
元件分类: EEPROM
英文描述: 2K Microwire Compatible Serial EEPROM
中文描述: 2K微丝兼容串行EEPROM
文件页数: 6/12页
文件大小: 222K
代理商: 93LC56AP
93LC46/56/66
1997 Microchip Technology Inc.
DS11168L-page 3
2.0
PIN DESCRIPTION
2.1
Chip Select (CS)
A high level selects the device. A low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2
Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93LCXX.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specied num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1 to Table 2-6). CLK and DI then become don't
care inputs waiting for a new START condition to be
detected.
2.3
Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out (DO)
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (TPD after the posi-
tive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation has
been initiated.
The status signal is not available on DO, if CS is held
low or high during the entire WRITE or ERASE cycle. In
all other cases DO is in the HIGH-Z mode. If status is
checked after the ERASE/WRITE cycle, a pull-up
resistor on DO is required to read the READY signal.
2.5
Organization (ORG)
When ORG is tied to VSS, the (x8) memory organiza-
tion is selected. When ORG is connected to Vcc or
oated, the (x16) memory organization is selected.
ORG can only be oated for clock speeds of 1 MHz or
less for the (X16) memory organization. For clock
speeds greater than 1 MHz, ORG must be tied to Vcc
or VSS.
Note:
CS must go low between consecutive
instructions.
相关PDF资料
PDF描述
93LC56ASN 2K Microwire Compatible Serial EEPROM
93LC56AST 2K Microwire Compatible Serial EEPROM
93LC56BMS 2K Microwire Compatible Serial EEPROM
93LC56BP 2K Microwire Compatible Serial EEPROM
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相关代理商/技术参数
参数描述
93LC56ASN 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:2K Microwire Compatible Serial EEPROM
93LC56AST 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:2K Microwire Compatible Serial EEPROM
93LC56AT/SN 功能描述:电可擦除可编程只读存储器 256x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93LC56AT/ST 功能描述:电可擦除可编程只读存储器 256x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93LC56AT-E/CH 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:1K-16K Microwire Compatible Serial EEPROMs