参数资料
型号: 93LC56ASN
厂商: Microchip Technology Inc.
元件分类: EEPROM
英文描述: 2K Microwire Compatible Serial EEPROM
中文描述: 2K微丝兼容串行EEPROM
文件页数: 8/12页
文件大小: 222K
代理商: 93LC56ASN
93LC46/56/66
1997 Microchip Technology Inc.
DS11168L-page 5
3.0
FUNCTIONAL DESCRIPTION
When it is connected to ground, the (x8) organization is
selected. When the ORG pin is connected to Vcc, the
(x16) organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a HIGH-Z state, except when reading data from the
device or when checking the READY/BUSY status dur-
ing a programming operation. The READY/BUSY
status can be veried during an ERASE/WRITE opera-
tion by polling the DO pin; DO low indicates that pro-
gramming is still in progress, while DO high indicates
the device is ready. The DO will enter the HIGH-Z state
on the falling edge of the CS.
3.1
START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the rst time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed
if
the
required
amount
of
opcodes,
addresses, and data bits for any particular instruction is
clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new START condition is
detected.
3.2
Data In (DI) and Data Out (DO)
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this conguration, if
A0 is a logic-high level, it is possible for a “bus conict”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition the voltage
level seen at DO is undened and will depend upon the
relative impedances of Data Out, and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the DO pin.
3.3
Data Protection
During power-up, all programming modes of operation
are inhibited until Vcc has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 1.4V at nominal conditions.
The ERASE/WRITE Disable (EWDS) and ERASE/
WRITE Enable (EWEN) commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
FIGURE 3-1:
SYNCHRONOUS DATA TIMING
CLK
STATUS VALID
VIH
VIL
CS
TCSS
TDIS
TDIH
TSV
TCSH
TCKH
TCKL
TPD
TCZ
TPD
VIH
VIL
DI
VIH
VIL
DO
(READ)
VOH
VOL
DO
(PROGRAM)
VOH
VOL
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