参数资料
型号: 93LC56B-I/SNA27
元件分类: PROM
英文描述: 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封装: 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8
文件页数: 29/30页
文件大小: 551K
代理商: 93LC56B-I/SNA27
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
DS21794F-page 8
2008 Microchip Technology Inc.
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
VCC must be
≥4.5V for proper operation of ERAL.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
TCSL
Check Status
10
0
1
0
x
x
TSV
TCZ
Busy
Ready
High-Z
TEC
High-Z
VCC must be
≥4.5V for proper operation of ERAL.
CS
CLK
DI
DO
TCSL
Check Status
10
0
1
0
x
x
TSV
TCZ
Busy
Ready
High-Z
TEC
High-Z
相关PDF资料
PDF描述
93C56A-E/PG 256 X 8 MICROWIRE BUS SERIAL EEPROM, PDIP8
93C56B-I/PG 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDIP8
93C56AXT-E/OT 256 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO6
93C56CX-I/P 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDIP8
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