参数资料
型号: 93LC66BT/SL
元件分类: PROM
英文描述: 256 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO14
封装: 0.150 INCH, PLASTIC, SOIC-14
文件页数: 5/10页
文件大小: 126K
代理商: 93LC66BT/SL
93LC46B/56B/66B
DS20068F-page 4
1995 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The
DO pin is normally held in a high-Z state except when
reading data from the device, or when checking the
ready/busy status during a programming operation.
The ready/busy status can be veried during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. The DO will enter the
high-Z state on the falling edge of the CS.
2.1
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the rst time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this conguration it is possible
for a “bus conict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undened and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
2.3
Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V at nominal conditions.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
3.0
READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) output
string. The output data bits will toggle on the rising
edge of the CLK and are stable after the specied time
delay (TPD). Sequential read is possible when CS is
held high. The memory data will automatically cycle to
the next register and output sequentially.
4.0
ERASE/WRITE ENABLE AND
DISABLE
The 93LC46B/56B/66B powers up in the Erase/Write
Disable (EWDS) state. All programming modes must
be preceded by an Erase/Write Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruc-
tion is executed or VCC is removed from the device. To
protect against accidental data disturb, the EWDS
instruction can be used to disable all Erase/Write func-
tions and should follow all programming operations.
Execution of a READ instruction is independent of both
the EWEN and EWDS instructions.
5.0
ERASE
The ERASE instruction forces all data bits of the spec-
ied address to the logical "1" state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical "0" indicates that program-
ming is still in progress. DO at logical "1" indicates that
the register at the specied address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word (Typical).
6.0
WRITE
The WRITE instruction is followed by 16 bits of data
which are written into the specied address. After the
last data bit is put on the DI pin, CS must be brought
low before the next rising edge of the CLK clock. This
falling edge of CS initiates the self-timed auto-erase
and programming cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is com-
plete. DO at logical "0" indicates that programming is
still in progress. DO at logical "1" indicates that the reg-
ister at the specied address has been written with the
data specied and the device is ready for another
instruction.
The WRITE cycle takes 4 ms per word (Typical).
相关PDF资料
PDF描述
93LC66BT-I/SL 256 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO14
93LC56B-I/SL 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO14
93LC56BT/SL 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO14
93LC66B/SL 256 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO14
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93LC66BX-E/SN 功能描述:电可擦除可编程只读存储器 256x16 Rot Pin RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93LC66BX-E/SNG 功能描述:电可擦除可编程只读存储器 256x16 Rot Pin Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93LC66BX-I/SN 功能描述:电可擦除可编程只读存储器 256x16 Rot Pin RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
93LC66BX-I/SNG 功能描述:电可擦除可编程只读存储器 256x16 Rot Pin Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8