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参数资料
| 型号： | 950211BFL-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, MO-118, SSOP-56 |
| 文件页数： | 9/23页 |
| 文件大小： | 214K |
| 代理商： | 950211BFL-T |
17
Integrated
Circuit
Systems, Inc.
ICS950211
0465E—05/17/05
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66
PCICLK_F and PCICLK
Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3V66
3V66 pin to pin skew
0
155
500
ps
PCI
PCI_F and PCI pin to pin skew
0
302
500
ps
3V66 to PCI
S3V66-PCI
3V66 leads 33MHz PCI
1.5
1.7
3.5
ns
1Guaranteed by design, not 100% tested in production.
PD# Functionality
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相关PDF资料 |
PDF描述 |
|---|---|
| 950211BFLF | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 08053C103KA72A | General Specifications |
| 950211BFLFT | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 950211BFT | 205 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 08053C103KA74A | General Specifications |
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