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参数资料
| 型号： | 954204AGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56 |
| 文件页数： | 7/20页 |
| 文件大小： | 261K |
| 代理商： | 954204AGLFT |
15
Integrated
Circuit
Systems, Inc.
ICS954204
0933D—03/16/05
PCI_STOP#
CPU
CPU#
SRC
SRC#
PCIF/PCI
DOT
DOT#
USB
REF
0
Normal
33MHz
Normal
48MHz
14.318MHz
1
Normal
Iref*6 or Float
Low
Normal
48MHz
14.318MHz
PD
CPU
CPU#
SRC
SRC#
PCIF/PCI
DOT
DOT#
USB
REF
0
Normal
33MHz
Normal
Low
48MHz
14.318MHz
1
Iref*2 or Float
Float
Iref*2 or Float
Float
Low
Iref*2 or Float
Float
Low
Table 6: PD Functionality
Table 5: PCI_STOP# Functionality
PD
CPU_STOP#
CPU_STOP
Tristate BIT
PD Tristate BIT
10
54
B5b[6, 5, 4]
B5b[2,1,0]
CPU[2:0]
0
1
X
Running
CPU[2:0]
0
X
Running
Driven @ IREF X6
CPU[2:0]
0
1
X
Running
Tristate
CPU[2:0]
1
X
1
Driven @ IREF X2
CPU[2:0]
1
X
0
Tristate
PD
PCI/SRC_STOP#
PCI/SRC_STOP
Tristate BIT
PD Tristate BIT
10
55
B5b7
B5b3
SRC
0
1
X
Running
SRC
0
X
Running
Driven @ IREF X6
SRC
0
1
X
Running
Tristate
SRC
1
X
1
Driven @ IREF X2
SRC
1
X
0TristateTristate
Table 8: Tristate SRC Clock Control Truth Table
Signal
NON-STOP
OUTPUTS
STOPPABLE OUTPUTS
Signal
NON-STOP
OUTPUTS
Table 7: Tristate CPU Clock Control Truth Table
STOPPABLE OUTPUTS
PD
PD Tristate BIT
10
B4b6
DOT_96
0
X
Running
DOT_96
1
Driven @ IREF X2
DOT_96
1
0
Tristate
Table 9: Tristate DOT Clock Control Truth Table
Signal
STOPPABLE OUTPUTS
Table10: CLKREQ# Clock Control Truth Table
PD
PCI/SRC_STOP#
CLKREQA#
CLKREQB#
10
55
33, 32
SRC
0
1
0
Running
SRC
0
1
Tristate
SRC
0
Tristate
SRC
0
1
Stopped per B5b7
SRC
1
X
Stopped per B5b3
Signal
SELECTED OUTPUTS
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