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参数资料
| 型号： | 954206BFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.300 INCH, 0.025 INCH PITCH, M0-118N, SSOP-56 |
| 文件页数： | 7/20页 |
| 文件大小： | 315K |
| 代理商： | 954206BFT |
15
Integrated
Circuit
Systems, Inc.
ICS954206B
Advance Information
0940—06/23/05
I
2C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div7
RW
X
Bit 6
N Div6
RW
X
Bit 5
N Div5
RW
X
Bit 4
N Div4
RW
X
Bit 3
N Div3
RW
X
Bit 2
N Div2
RW
X
Bit 1
N Div1
RW
X
Bit 0
N Div0
RW
X
I
2C Table: Spread Spectrum Control Register
Control
Function
Bit 7
SSP7
RW
X
Bit 6
SSP6
RW
X
Bit 5
SSP5
RW
X
Bit 4
SSP4
RW
X
Bit 3
SSP3
RW
X
Bit 2
SSP2
RW
X
Bit 1
SSP1
RW
X
Bit 0
SSP0
RW
X
I
2C Table: Spread Spectrum Control Register
Control
Function
Bit 7
Reserved
R
0
Bit 6
SSP14
RW
X
Bit 5
SSP13
RW
X
Bit 4
SSP12
RW
X
Bit 3
SSP11
RW
X
Bit 2
SSP10
RW
X
Bit 1
SSP9
RW
X
Bit 0
SSP8
RW
X
I
2C Table: Output Divider Control Register
Control
Function
Bit 7
PCIEX Div3
RW
0000:/2
0100:/4
1000:/8
1100:/16
X
Bit 6
PCIEX Div2
RW
0001:/3
0101:/6
1001:/12
1101:/24
X
Bit 5
PCIEX Div1
RW
0010:/5
0110:/10 1010:/20
1110:/40
X
Bit 4
PCIEX Div0
RW
0011:/15
0111:/30 1011:/60 1111:/120
X
Bit 3
CPU Div3
RW
0000:/2
0100:/4
1000:/8
1100:/16
X
Bit 2
CPU Div2
RW
0001:/3
0101:/6
1001:/12
1101:/24
X
Bit 1
CPU Div1
RW
0010:/5
0110:/10 1010:/20
1110:/40
X
Bit 0
CPU Div0
RW
0011:/15
0111:/30 1011:/60 1111:/120
X
0
-
Type
1
Type
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
1
Spread Spectrum
Programming b(7:0)
N Divider Programming
b(8:0)
1
Byte 12
-
CPUDivider Ratio
Programming Bits
PCIEX Divider Ratio
Programming Bits
PWD
Name
Type
0
PWD
Name
Type
Name
PWD
0
-
Name
Pin #
-
PWD
0
Byte 13
Pin #
-
Byte 14
Pin #
-
Pin #
-
Byte 15
-
Spread Spectrum
Programming b(14:8)
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
-
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