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| 型号： | 97ULPA877AHLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封装： | ROHS COMPLIANT, PLASTIC, MO-225/205, VFBGA-52 |
| 文件页数： | 4/15页 |
| 文件大小： | 183K |
| 代理商： | 97ULPA877AHLF-T |
12
ICS97ULPA877A
1088B—01/18/06
Figure 11. AVDD Filtering
- Place the 2200pF capacitor close to the PLL.
- Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one
GND via (farthest from PLL).
- Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
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