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参数资料
| 型号： | 9DB102BFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SSOP-20 |
| 文件页数： | 6/13页 |
| 文件大小： | 150K |
| 代理商： | 9DB102BFLF |
IDT
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV N 04/20/11
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
2
Pin Configuration
20-pin SSOP & TSSOP
VDD
GND
5,9,12,16
6,15
PCI Express Outputs
96
SMBUS
20
19
IREF
20
19
Analog VDD & GND for PLL core
Description
Pin Number
Power Groups
Pin Description
PLL_BW 1
20 VDDA
CLK_INT 2
19 GNDA
C LK_INC 3
18 IREF
vCLKREQ0# 4
17 vC LKREQ1#
VDD 5
16 VDD
GND 6
15 GND
PCIEXT0 7
14 PCIEXT1
PCIEXC0 8
13 PCIEXC1
VDD 9
12 VDD
SMBDAT 10
11 SMBCLK
IC
S
9
DB
1
0
2
Note: Pins preceeded by ' v ' have internal
120K ohm pull down resistors
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
PLL_BW
IN
3.3V input for selecting PLL Band Width
0 = low, 1= high
2
CLK_INT
IN
True Input for differential reference clock.
3
CLK_INC
IN
Complementary Input for differential reference clock.
4
v CLKREQ0#
IN
Output enable for PCI Expres s output pair 0.
0 = enabled, 1 =disabled
5
VDD
PWR
Power supply , nominal 3.3V
6
GND
PWR
Ground pin.
7
PCIEXT0
OUT
True clock of differential PCI_Express pair.
8
PCIEXC0
OUT
Complementary clock of differential PCI_Express pair.
9
VDD
PWR
Power supply , nominal 3.3V
10
SMBDAT
I/O
Data pin of SMBUS c ircuitry, 5V tolerant
11
SMBCLK
IN
Clock pin of SMBUS c ircuitry, 5V tolerant
12
VDD
PWR
Power supply , nominal 3.3V
13
PCIEXC1
OUT
Complementary clock of differential PCI_Express pair.
14
PCIEXT1
OUT
True clock of differential PCI_Express pair.
15
GND
PWR
Ground pin.
16
VDD
PWR
Power supply , nominal 3.3V
17
v CLKREQ1#
IN
Output enable for PCI Expres s output pair 1.
0 = enabled, 1 =disabled
18
IREF
OUT
This pin establishes the reference for the differential current-mode
output pairs. It requires a fix ed precision resistor to ground. 475ohm is
the standard value for 100ohm differential impedance. Other
impedanc es require different values. See data sheet.
19
GNDA
PWR
Ground pin for the PLL c ore.
20
VDDA
PWR
3.3V power for the PLL core.
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
Note:
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB102BFLFT | 功能描述:时钟缓冲器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB102BGILF | 功能描述:时钟缓冲器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB102BGILFT | 功能描述:时钟缓冲器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB102BGLF | 功能描述:时钟缓冲器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB102BGLFT | 功能描述:时钟缓冲器 2 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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