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参数资料
| 型号： | 9DB803DFILFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件页数： | 15/21页 |
| 文件大小： | 174K |
| 代理商： | 9DB803DFILFT |
IDTTM/ICSTM
Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803D
REV K 05/09/11
ICS9DB803D
Eight Output Differential Buffer for PCIe for Gen 2
3
Pin Description for OE_INV = 0
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
SRC_DIV#
IN
Active low Input for determining SRC output frequency SRC or SRC/2.
0 = SRC/2, 1= SRC
2
VDDR
PWR
3.3V power for differential input clock (receiver). This VDD should be
treated as an analog power rail and filtered appropriately.
3
GND
PWR
Ground pin.
4
SRC_IN
IN
0.7 V Differential SRC TRUE input
5
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
6OE_0
IN
Active high input for enabling output 0.
0 =disable outputs, 1= enable outputs
7OE_3
IN
Active high input for enabling output 3.
0 =disable outputs, 1= enable outputs
8
DIF_0
OUT
0.7V differential true clock output
9
DIF_0#
OUT
0.7V differential Complementary clock output
10
GND
PWR
Ground pin.
11
VDD
PWR
Power supply, nominal 3.3V
12
DIF_1
OUT
0.7V differential true clock output
13
DIF_1#
OUT
0.7V differential Complementary clock output
14
OE_1
IN
Active high input for enabling output 1.
0 =disable outputs, 1= enable outputs
15
OE_2
IN
Active high input for enabling output 2.
0 =disable outputs, 1= enable outputs
16
DIF_2
OUT
0.7V differential true clock output
17
DIF_2#
OUT
0.7V differential Complementary clock output
18
GND
PWR
Ground pin.
19
VDD
PWR
Power supply, nominal 3.3V
20
DIF_3
OUT
0.7V differential true clock output
21
DIF_3#
OUT
0.7V differential Complementary clock output
22
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
24
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
相关PDF资料 |
PDF描述 |
|---|---|
| 9DB803DGILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB803DFLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB803DFLFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB803DGILF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB803DGILFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB803DGLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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