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参数资料
| 型号： | 9DB833AFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | ROHS COMPLIANT, SSOP-48 |
| 文件页数： | 15/18页 |
| 文件大小： | 226K |
| 代理商： | 9DB833AFLF |
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
6
9DB833
REV C 052411
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS N OTES
T
COM
C ommmercial range
0
70
°C
1
TIND
Industrial range
-40
85
°C
1
Input High Voltage
V
IH
Single-ended inputs, except SMBus, low threshold
and tri-level inputs
2
V
DD + 0.3
V1
Input Low Voltage
V
IL
Single-ended inputs, except SMBus, low threshold
and tri-level inputs
GND - 0.3
0.8
V
1
IIN
Single-ended inputs, VIN = GND, VIN = VDD
-5
5
uA
1
IINP
Single-ended inputs
V
IN = 0 V; I nputs with interna l pu ll-u p resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
1
Fibyp
VDD = 3.3 V, Bypass mode
5
166
MHz
2
F
ip ll
V
DD = 3.3 V, 10 0MHz P LL m ode
50
100.00
110
MHz
2
Pin Inductance
Lpin
7nH
1
C
IN
Logic Inputs, except DIF_IN
1.5
5
pF
1
CINDIF_IN
DIF_IN differential clock inputs
1.5
2.7
pF
1,4
COUT
Output pin capacitance
6
pF
1
C lk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms
1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33
kHz
1
OE# Latency
tLATOE#
D IF start after OE# assertion
DIF stop after OE# deassertion
1
3
cycles
1,3
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
t
F
Fall time of control inputs
5
ns
1,2
Trise
t
R
R ise time of control inputs
5
ns
1,2
SMBus Input Low Voltage
VIL SMB
0.8
V
1
SMBus Input High Voltage
V
IHSM B
2.1
V
DD SMB
V1
SMBus Output Low Voltage
VOL SMB
@ IPULLUP
0.4
V
1
SMBus Sink Current
IPULLUP
@ VOL
4mA
1
Nominal Bus Voltage
VDDSMB
3V to 5V +/- 10%
2.7
5.5
V
1
SCLK/SD ATA Rise Time
t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA Fall Time
t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
SMBus Operating Frequency
fMAX SMB
Maximum SMBus operating frequency
100
kHz
1,5
1
Guaranteed by design and characterization, not 100% tested in production.
2
C ontrol input must be monotonic from 20% to 80% of input swing.
5The differential input clock must be running for the SMBus to be active
Ambient Operating
Temperature
Input Current
3Time from deassertion until outputs are >200 mV
4DIF_IN input
Capacitance
Input Frequency
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB833AFLFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB833AGILF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB833AGILFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB833AGLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB833AGLFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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