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参数资料
| 型号： | 9FG1201HFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件页数： | 17/23页 |
| 文件大小： | 268K |
| 代理商： | 9FG1201HFLF |
IDTTM/ICSTM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
3
Pin Description
Power Groups
VDD
GND
56
55
Main PLL, Analog
11,22,38,50 12,23,37,49
DIF clocks
Description
Pin Number
Pin # Pin Name
Type
Pin Description
1HIGH_BW#
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
2
CLK_IN
IN
Input for reference clock.
3
CLK_IN#
IN
"Complementary" reference clock input.
4
SMB_A0
IN
SMBus address bit 0 (LSB)
5OE0#
IN
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
6
DIF_0
OUT
0.7V differential true clock output
7
DIF_0#
OUT
0.7V differential complement clock output
8OE1#
IN
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
9
DIF_1
OUT
0.7V differential true clock output
10
DIF_1#
OUT
0.7V differential complement clock output
11
VDD
PWR
Power supply, nominal 3.3V
12
GND
PWR
Ground pin.
13
DIF_2
OUT
0.7V differential true clock output
14
DIF_2#
OUT
0.7V differential complement clock output
15
OE2#
IN
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
16
DIF_3
OUT
0.7V differential true clock output
17
DIF_3#
OUT
0.7V differential complement clock output
18
OE3#
IN
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
19
DIF_4
OUT
0.7V differential true clock output
20
DIF_4#
OUT
0.7V differential complement clock output
21
OE4#
IN
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
22
VDD
PWR
Power supply, nominal 3.3V
23
GND
PWR
Ground pin.
24
DIF_5
OUT
0.7V differential true clock output
25
DIF_5#
OUT
0.7V differential complement clock output
26
OE5#
IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
27
SMB_A1
IN
SMBus address bit 1
28
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
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