参数资料
型号: 9FG830AGILFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
文件页数: 8/19页
文件大小: 219K
代理商: 9FG830AGILFT
IDT Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
1680C—08/26/10
9FG830
Eight Output Differential Frequency Generator for PCIe Gen3 and QPI
16
SMBus Table: PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL N Div7
RW
X
Bit 6
PLL N Div6
RW
X
Bit 5
PLL N Div5
RW
X
Bit 4
PLL N Div4
RW
X
Bit 3
PLL N Div3
RW
X
Bit 2
PLL N Div2
RW
X
Bit 1
PLL N Div1
RW
X
Bit 0
PLL N Div0
RW
X
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL SSP7
RW
X
Bit 6
PLL SSP6
RW
X
Bit 5
PLL SSP5
RW
X
Bit 4
PLL SSP4
RW
X
Bit 3
PLL SSP3
RW
X
Bit 2
PLL SSP2
RW
X
Bit 1
PLL SSP1
RW
X
Bit 0
PLL SSP0
RW
X
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
PLL SSP14
RW
X
Bit 5
PLL SSP13
RW
X
Bit 4
PLL SSP12
RW
X
Bit 3
PLL SSP11
RW
X
Bit 2
PLL SSP10
RW
X
Bit 1
PLL SSP9
RW
X
Bit 0
PLL SSP8
RW
X
Byte 11
-
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
Byte 12
-
N Divider Programming
Byte11 bit(7:0) and
Byte10 bit(7:6)
-
Spread Spectrum
Programming bit(7:0)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
Byte 13
-
Reserved
-
Spread Spectrum
Programming bit(14:8)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
相关PDF资料
PDF描述
9FG830AGILF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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9FG830AFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9FG830AGLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
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