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参数资料
型号： 9LPRS502YGLFT
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 微控制器/微处理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封装： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件页数： 13/29页
文件大小： 279K
代理商： 9LPRS502YGLFT
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
20
Byte 0 FS Readback and PLL Selection Register
Bit
Pin
Name
Description
Type
Default
7
-
FSLC
CPU Freq. Sel. Bit (Most Significant)
R
Latch
6
-
FSLB
CPU Freq. Sel. Bit
R
Latch
5
-
FSLA
CPU Freq. Sel. Bit (Least Significant)
R
Latch
4-
iAMT_EN
Set via SMBus or dynamically by CK505 if detects
dynamic M1
RW
0
3
Reserved
RW
0
2
-
SRC_Main_SEL
Select source for SRC Main
RW
0
1
-
SATA_SEL
Select source for SATA clock
RW
0
0-
PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-on
and go to latches open state
This bit is ignored and treated at '1' if device is in iAMT
mode.
RW
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit
Pin
Name
Description
Type
Default
7
13/14
SRC0_SEL
Select SRC0 or DOT96
RW
0
6
-
PLL1_SSC_SEL
Select 0.5% down or center SSC
RW
0
5
PLL3_SSC_SEL
Select 0.5% down or center SSC
RW
0
4
PLL3_CF3
PLL3 Quick Config Bit 3
RW
0
3
PLL3_CF2
PLL3 Quick Config Bit 2
RW
0
2
PLL3_CF1
PLL3 Quick Config Bit 1
RW
0
1
PLL3_CF0
PLL3 Quick Config Bit 0
RW
1
0
PCI_SEL
RW
1
Byte 2 Output Enable Register
Bit
Pin
Name
Description
Type
Default
7
REF_OE
Output enable for REF, if disabled output is tri-stated
RW
1
6
USB_OE
Output enable for USB
RW
1
5
PCIF5_OE
Output enable for PCI5
RW
1
4
PCI4_OE
Output enable for PCI4
RW
1
3
PCI3_OE
Output enable for PCI3
RW
1
2
PCI2_OE
Output enable for PCI2
RW
1
PCI1_OE
Output enable for PCI1
RW
1
0
PCI0_OE
Output enable for PCI0
RW
1
Byte 3 Output Enable Register
Bit
Pin
Name
Description
Type
Default
7
SRC11_OE
Output enable for SRC11
RW
1
6
SRC10_OE
Output enable for SRC10
RW
1
5
SRC9_OE
Output enable for SRC9
RW
1
4
SRC8/ITP_OE
Output enable for SRC8 or ITP
RW
1
3
SRC7_OE
Output enable for SRC7
RW
1
2
SRC6_OE
Output enable for SRC6
RW
1
SRC5_OE
Output enable for SRC5
RW
1
0
SRC4_OE
Output enable for SRC4
RW
1
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit
Pin
Name
Description
Type
Default
7
SRC3_OE
Output enable for SRC3
RW
1
6
SATA/SRC2_OE
Output enable for SATA/SRC2
RW
1
5
SRC1_OE
Output enable for SRC1
RW
1
4
SRC0/DOT96_OE
Output enable for SRC0/DOT96
RW
1
3
CPU1_OE
Output enable for CPU1
RW
1
2
CPU0_OE
Output enable for CPU0
RW
1
PLL1_SSC_ON
Enable PLL1's spread modulation
RW
1
0
PLL3_SSC_ON
Enable PLL3's spread modulation
RW
1
Spread Enabled
1
Output Disabled
Spread Disabled
Output Enabled
Spread Enabled
Output Disabled
Output Enabled
0
01
Output Disabled
Output Enabled
Output Disabled
1
Output Disabled
Output Enabled
Output Disabled
0
Output Disabled
0
Down spread
See Table 2: PLL3 Quick Configuration
Only applies if Byte 0, bit 2 = 0.
DOT96
Center spread
SRC0
01
1
SATA = SRC_Main
Configuration Not Saved
iAMT Enabled
SRC Main = PLL3
See Table 1 : CPU Frequency Select Table
Legacy Mode
SRC Main = PLL1
Configuration Saved
SATA = PLL2
PCI from PLL1
PCI from SRC_MAIN
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相关代理商/技术参数
参数描述
9LPRS502YKLFT 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
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9LPRS511EGLF 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel
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