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参数资料
| 型号： | 9LPRS525AFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件页数： | 6/21页 |
| 文件大小： | 200K |
| 代理商： | 9LPRS525AFLFT |
IDTTM
PC MAIN CLOCK
1484D—01/31/11
ICS9LPRS525
PC MAIN CLOCK
14
Byte 0 FS Readback and PLL Selection Register
Bit
Pin
Name
Description
Type
0
1
Default
7
-
FSLC
CPU Freq. Sel. Bit (Most Significant)
R
Latch
6
-
FSLB
CPU Freq. Sel. Bit
R
Latch
5
-
FSLA
CPU Freq. Sel. Bit (Least Significant)
R
Latch
4-
iAMT_EN
Set via SMBus or dynamically by CK505 if detects
dynamic M1
RW
Legacy Mode
iAMT Enabled
0
3
Reserved
RW
0
2
-
SRC_Main_SEL
Select source for SRC Main
RW SRC Main = PLL1 SRC Main = PLL3 Latch
1
-
SATA_SEL
Select source for SATA clock
RW
SATA =
SRC_Main
SATA = PLL2
0
0-
PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-
on and go to latches open state
This bit is ignored and treated at '1' if device is in
iAMT mode.
RW
Configuration Not
Saved
Configuration
Saved
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit
Pin
Name
Description
Type
0
1
Default
7
13/14
SRC0_SEL
Select SRC0 or DOT96
RW
SRC0
DOT96
0
6
-
PLL1_SSC_SEL
Select 0.5% down or center SSC
RW
Down spread
Center spread
Latch
5
PLL3_SSC_SEL
Select 0.5% down or center SSC
RW
Down spread
Center spread
0
4
PLL3_CF3
PLL3 Quick Config Bit 3
RW
0
3
PLL3_CF2
PLL3 Quick Config Bit 2
RW
0
2
PLL3_CF1
PLL3 Quick Config Bit 1
RW
0
1
PLL3_CF0
PLL3 Quick Config Bit 0
RW
1
0
PCI_SEL
RW
PCI from PLL1
PCI from
SRC_MAIN
1
Byte 2 Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7REF_OE
Output enable for REF, if disabled output is tri-
stated
RW
Output Disabled
Output Enabled
1
6
USB_OE
Output enable for USB
RW
Output Disabled
Output Enabled
1
5
PCIF5_OE
Output enable for PCI5
RW
Output Disabled
Output Enabled
1
4
PCI4_OE
Output enable for PCI4
RW
Output Disabled
Output Enabled
1
3
PCI3_OE
Output enable for PCI3
RW
Output Disabled
Output Enabled
1
2
PCI2_OE
Output enable for PCI2
RW
Output Disabled
Output Enabled
1
PCI1_OE
Output enable for PCI1
RW
Output Disabled
Output Enabled
1
0
PCI0_OE
Output enable for PCI0
RW
Output Disabled
Output Enabled
1
Byte 3 Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
Reserved
RW
-
1
6
Reserved
RW
-
1
5
Reserved
RW
-
1
4
SRC8/ITP_OE
Output enable for SRC8 or ITP
RW
Output Disabled
Output Enabled
1
3
SRC7_OE
Output enable for SRC7
RW
Output Disabled
Output Enabled
1
2
SRC6_OE
Output enable for SRC6
RW
Output Disabled
Output Enabled
1
SRC5_OE
Output enable for SRC5
RW
Output Disabled
Output Enabled
1
0
SRC4_OE
Output enable for SRC4
RW
Output Disabled
Output Enabled
1
See Table 1 : CPU Frequency Select
Table
See Table 2: PLL3 Quick
Configuration
Only applies if Byte 0, bit 2 = 0.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9LPRS525AGILF | 功能描述:时钟合成器/抖动清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9LPRS525AGILFT | 功能描述:时钟合成器/抖动清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9LPRS525AGLF | 功能描述:时钟合成器/抖动清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9LPRS525AGLFT | 功能描述:时钟合成器/抖动清除器 56-PIN CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9LPRS535 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:48-pin CK505 for Intel Systems |
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