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参数资料
| 型号： | 9LPRS535BFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 封装： | 0.300 INCH, MO-118, SSOP-48 |
| 文件页数： | 6/17页 |
| 文件大小： | 216K |
| 代理商： | 9LPRS535BFLFT |
14
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
Datasheet
1461A—07/28/09
Test Clarification Table
Comments
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MOD
E
HW PIN
TEST
ENTRY BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
<2.0V
X
0
NORMAL
>2.0V
0
X
0
HI-Z
>2.0V
0
X
1
REF/N
>2.0V
1
X
0
REF/N
>2.0V
1
X
1
REF/N
<2.0V
X
1
0
HI-Z
<2.0V
X
1
REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
HW
SW
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V then use TEST_SEL
If power-up w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
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相关代理商/技术参数 |
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|---|---|
| 9LPRS535BGLF | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9LPRS535BGLFT | 制造商:Integrated Device Technology Inc 功能描述:48-PIN CK505 FOR INTEL SYSTEMS 制造商:Integrated Device Technology Inc 功能描述:48 TSSOP (LEAD FREE) - Tape and Reel |
| 9LPRS535CFLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:48-pin CK505 for Intel Systems |
| 9LPRS535CFLFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:48-pin CK505 for Intel Systems |
| 9LPRS535CGLF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:48-pin CK505 for Intel Systems |
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