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参数资料
| 型号： | 9LPRS545CGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件页数： | 14/17页 |
| 文件大小： | 215K |
| 代理商： | 9LPRS545CGLFT |
6
Integrated
Circuit
Systems, Inc.
ICS9LPRS545
Datasheet
1479A—07/28/09
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Ambient Operating Temp
Tambient
-
0
70
°C
Supply Voltage
VDDxxx
Supply Voltage
3.135
3.465
V
Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
0.9975
3.465
V
10
Input High Voltage
VIHSE
Single-ended 3.3V inputs
2
VDD + 0.3
V
3
Input Low Voltage
VILSE
Single-ended 3.3V inputs
VSS - 0.3
0.8
V
3
Low Threshold Input- High Voltage
VIH_FS_TEST
3.3 V +/-5%
2
VDD + 0.3
V
8
Low Threshold Input- FSC = '1' Voltage
VIH_FS_FSC
3.3 V +/-5%
0.7
1.5
V
8
Low Threshold Input- FSA,FSB = '1'
Voltage
VIH_FS_FSAB
3.3 V +/-5%
0.7
VDD+0.3
V
Low Threshold Input-Low Voltage
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
5
uA
2
Input Leakage Current
IINRES
Inputs with pull up or pull down resistors
VIN = VDD , VIN = GND
-200
200
uA
Output High Voltage
VOHSE
Single-ended outputs, IOH = -1mA
2.4
V
1
Output Low Voltage
VOLSE
Single-ended outputs, IOL = 1 mA
0.4
V
1
IDDOP3.3
Full Active, CL = Full load; Idd 3.3V
125
mA
IDDOPIO
Full Active, CL = Full load; IDD IO
50
mA
10
IDDiAMT3.3
M1 mode, 3.3V Rail
40
mA
IDDiAMTIO
M1 Mode, IO Rail
10
mA
IDDPD3.3
Power down mode, 3.3V Rail
5
mA
IDDPDIO
Power down mode, IO Rail
0.1
mA
10
Input Frequency
Fi
VDD = 3.3 V
15
MHz
Pin Inductance
Lpin
7
nH
CIN
Logic Inputs
1.5
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
6
pF
Clk Stabilization
TSTAB
From VDD Power-Up or de-assertion of PD to 1st
clock
1.8
ms
Tdrive_CR_off
TDRCROFF
Output stop after CR deasserted
400
ns
Tdrive_CR_on
TDRCRON
Output run after CR asserted
0
us
Tdrive_CPU
TDRSRC
CPU output enable after
PCI_STOP# de-assertion
10
ns
Tfall_SE
TFALL
10
ns
Trise_SE
TRISE
10
ns
SMBus Voltage
VDD
2.7
5.5
V
Low-level Output Voltage
VOLSMB
@ IPULLUP
0.4
V
Current sinking at VOLSMB = 0.4 V
IPULLUP
SMB Data Pin
4
mA
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
Maximum SMBus Operating Frequency
FSMBUS
100
kHz
Spread Spectrum Modulation Frequency
fSSMOD
Triangular Modulation
30
33
kHz
1Signal is required to be monotonic in this region.
2 input leakage current does not include inputs with pull-up or pull-down resistors
4 Intentionally blank
7 Operation under these conditions is neither implied, nor guaranteed.
8 Frequency Select pins which have tri-level input
9 PCI3/CFG0 is optional
10 If present. Not all parts have this feature.
Operating Supply Current
iAMT Mode Current
Powerdown Current
Input Capacitance
Fall/rise time of all 3.3V control inputs from 20-80%
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.
5 Maximum VIH is not to exceed VDD
6 Human Body Model
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