- 您现在的位置：买卖IC网 > PDF目录25570 > 9P935AFLF (INTEGRATED DEVICE TECHNOLOGY INC) 9P SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 PDF资料下载
参数资料
| 型号： | 9P935AFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9P SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件页数： | 6/13页 |
| 文件大小： | 191K |
| 代理商： | 9P935AFLF |
IDTTM/ICSTM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
REV H
12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
2
Pin Description
Pin#
Pin Name
Type
Pin Description
1
DDRC0
OUT
"Complementary" Clock of differential pair output.
2
DDRT0
OUT
"True" Clock of differential pair output.
3
VDD2.5/1.8
PWR
Power supply, nominal 2.5V or 1.8V
4
DDRT1
OUT
"True" Clock of differential pair output.
5
DDRC1
OUT
"Complementary" Clock of differential pair output.
6
GND
PWR
Ground pin.
7
VDDA2.5/1.8
PWR
Output power supply, nominal 2.5V or 1.8V
8
GND
PWR
Ground pin.
9
CLK_INT
IN
"True" reference clock input.
10
CLK_INC
IN
"Complementary" reference clock input.
11
VDD2.5/1.8
PWR
Power supply, nominal 2.5V or 1.8V
12
DDRT2
OUT
"True" Clock of differential pair output.
13
DDRC2
OUT
"Complementary" Clock of differential pair output.
14
GND
PWR
Ground pin.
15
DDRC3
OUT
"Complementary" Clock of differential pair output.
16
DDRT3
OUT
"True" Clock of differential pair output.
17
FB_OUT
OUT
Feedback output, dedicated for external feedback.
18
FB_IN
IN
Single-ended feedback input, provides feedback signal to internal PLL to eliminate
phase error with the input clock.
19
SCLK
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
20
SDATA
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
21
VDD2.5/1.8
PWR
Power supply, nominal 2.5V or 1.8V
22
DDRT4
OUT
"True" Clock of differential pair output.
23
DDRC4
OUT
"Complementary" Clock of differential pair output.
24
GND
PWR
Ground pin.
25
VDD2.5/1.8
PWR
Power supply, nominal 2.5V or 1.8V
26
DDRT5
OUT
"True" Clock of differential pair output.
27
DDRC5
OUT
"Complementary" Clock of differential pair output.
28
GND
PWR
Ground pin.
相关PDF资料 |
PDF描述 |
|---|---|
| 9P935AGLFT | 9P SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9P20S | ACTIVE DELAY LINE, TRUE OUTPUT, PDIP8 |
| 9P35S | ACTIVE DELAY LINE, TRUE OUTPUT, PDIP8 |
| 9P5S | ACTIVE DELAY LINE, TRUE OUTPUT, PDIP8 |
| 9P50S | ACTIVE DELAY LINE, TRUE OUTPUT, PDIP8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9P935AFLFT | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9P935AGLF | 功能描述:延迟线/计时元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| 9P935AGLFT | 功能描述:延迟线/计时元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| 9P936AFLF | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9P936AFLFT | 功能描述:时钟驱动器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。