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参数资料
| 型号： | 9P935AGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9P SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封装： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28 |
| 文件页数： | 11/13页 |
| 文件大小： | 191K |
| 代理商： | 9P935AGLFT |
IDTTM/ICSTM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
REV H
12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
7
Recommended Operating Condition (see note 1)
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required
for switching, where VT is the true input level and VCP is the complementary input level.
4.
Differential cross-point voltage is expected to track variations of VDD and is the voltage
at which the differential signal must be crossing.
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD, AVDD
2.3
2.5
2.7
V
DDRT,DDRC
0.4
VDD/2 - 0.18
V
DDRT,DDRC
VDD/2 + 0.18
2.1
V
DC input signal voltage
(note 2)
VIN
-0.3
VDD + 0.3
V
DC - DDRT
0.36
VDD + 0.6
V
AC - DDRT
0.7
VDD + 0.6
V
Output differential cross-
voltage (note 4)
VOX
VDD/2 - 0.15
VDD/2 + 0.15
V
Input differential cross-
voltage (note 4)
VIX
VDD/2 - 0.2
VDD/2
VDD/2 + 0.2
V
High level output
current
IOH
-30
mA
Low level output current
IOL
-30
mA
Operating free-air
temperature
TA
085
°C
Differential input signal
voltage (note 3)
VID
Low level input voltage
VIL
High level input voltage
VIH
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