参数资料
型号: 9UMS9001AKLF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC56
封装: ROHS COMPLIANT, PLASTIC, MLF-56
文件页数: 8/15页
文件大小: 105K
代理商: 9UMS9001AKLF
IDT PC MAIN CLOCK - CK540
1247B—07/19/10
Advance Information
9UMS9001
PC MAIN CLOCK - CK540
2
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
X2
OUT Crystal output, nominally 14.318MHz.
2
X1
IN
Crystal input, Nominally 14.318MHz.
3
VDDREFIO_3.3
PWR Power pin for the REF output and crystal oscillator. 3.3V nominal.
4
REF0
OUT 3.3V 14.318MHz reference clock
5
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
6
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
7TEST_SEL
IN
3.3V input that puts the part in test mode. This is a realtime input. See the Test Clarification Table for
details.
8
TEST_MODE
IN
When Test mode is selected, this chooses either hi-Z or REF/N for the outputs.
9
PCI_STOP#
IN
3.3V tolerant input that stops all PCI and SRC clocks, except those set to be free running.
10
VDDIO_PCI3.3
PWR 3.3V power supply for the PCI outputs
11
PCI0
OUT 3.3V PCI clock output.
12
PCI1
OUT 3.3V PCI clock output.
13
PCI_F2
OUT Free running 3.3V PCI clock output
14
GNDPCI
PWR Ground for PCI output clocks.
15
GND48
PWR Ground for the USB clock.
16
USB_48MHz
OUT
Fixed 3.3V 48MHz USB clock output
17
VDD48IO_3.3
PWR 3.3V Power supply for the 48MHz output
18
VDD48PLL_3.3
PWR 3.3V Power supply for the 48/96MHz PLL
19
VDDIO_96Mhz
PWR Power supply for DOT96 output. VDD_IO = 1.05 to 3.3V +/-5%.
20
DOT96C_LPRS
OUT
Complement side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external
series resistor required).
21
DOT96T_LPRS
OUT
True side of low-power CK505-type 96MHz differential clock. Rs is integrated (No external series
resistor required).
22
GND
PWR Ground for 96MHz output
23
GND
PWR Ground for LCD 100 MHz output.
24
LCD100C_LPRS
OUT
Complement side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated
(No external series resistor required).
25
LCD100T_LPRS
OUT
True side of low-power CK505-type LCD100MHz spreading differential clock. Rs is integrated (No
external series resistor required).
26
VDDIO_LCD
PWR Power supply for LCD100 output. VDD_IO = 1.05 to 3.3V +/-5%.
27
VDDLCDPLL_3.3
PWR 3.3V Power supply for the LCD100 Spreading PLL
28
CLKREQ1#
IN
Clock request input for SRC output pair 1. See the SRC, LCD, DOT Power Management Table for
details
相关PDF资料
PDF描述
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