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参数资料
| 型号： | 9UMS9610CKLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC48 |
| 封装： | 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48 |
| 文件页数： | 18/20页 |
| 文件大小： | 134K |
| 代理商： | 9UMS9610CKLFT |
IDTTM/ICSTM PC MAIN CLOCK
1336—06/01/09
ICS9UMS9610
PC MAIN CLOCK
7
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
SMBus Voltage
V
DD
2.7
3.6
V
1
Low-level Output Voltage
V
OLSMB
@ I
PULLUP
0.4
V
1
Current sinking at
V
OLSMB = 0.4 V
I
PULLUP
SMB Data Pin
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
Maximum SMBus Operating
Frequency
F
SMBUS
Block Mode
100
kHz
1
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
7 Operation under these conditions is neither implied, nor guaranteed.
9 See PCI Clock-to-Clock Delay Figure
8 Maximum input voltage is not to exceed maximum VDD
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations.
Clock Periods Differential Outputs with Spread Spectrum Enabled
1 Clock
1us
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal
Maximum
SRC 100
9.87400
9.99900
10.00000
10.00100
10.05130
10.17630
ns
1,2
CPU 100
9.91400
9.99900
10.00000
10.00100
10.05130
10.13630
ns
1,2
CPU 133
7.41425
7.49925
7.50000
7.50075
7.53845
7.62345
ns
1,2
Clock Periods Differential Outputs with Spread Spectrum Disabled
1 Clock
1us
0.1s
1us
1 Clock
Lg-
-SSC
-ppm error
0ppm
+ ppm error
+SSC
Lg+
Absolute
Period
Short-term
Average
Long-Term
Average
Period
Long-Term
Average
Short-term
Average
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal
Maximum
SRC 100
9.87400
9.99900
10.00000
10.00100
10.17630
ns
1,2
CPU 100
9.91400
9.99900
10.00000
10.00100
10.13630
ns
1,2
CPU 133
7.41425
7.49925
7.50000
7.50075
7.62345
ns
1,2
DOT 96
10.16560
10.41560
10.41670
10.41770
10.66770
ns
1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Measurement Window
Units
Notes
Symbol
Definition
Si
g
n
a
l
Na
m
e
Si
g
n
a
l
Na
m
e
Notes
Symbol
Definition
Measurement Window
Units
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相关代理商/技术参数 |
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| 9UMS9633 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
| 9UMS9633BFILF | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 9UMS9633BFILFT | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 9UMS9633BFW3LFT | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:ULTRA MOBILE PC CLOCK FOR AUTOMOTIVE USE |
| 9UMS9633BKILF | 功能描述:时钟发生器及支持产品 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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