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| 型号： | A1182LUA-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/16页 |
| 文件大小： | 543K |
| 描述： | IC SWITCH HALL EFFECT UNI 3-SIP |
| 产品培训模块： | Current Sensor |
| 标准包装： | 500 |
| 传感范围： | 60G ~ 200G 跳闸 - 可编程，固定释放 |
| 类型： | 单极开关 |
| 电源电压： | 3.5 V ~ 24 V |
| 电流 - 电源： | 6.9mA |
| 输出类型： | 数字，开路集电极 |
| 特点： | 可编程 |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 3-SIP |
| 供应商设备封装： | 3-SIP |
| 包装： | 散装 |
Sensitive Two-Wire Field-Programmable
Chopper-Stabilized Unipolar Hall Effect Switches
A1180, A1181,
A1182, and A1183
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
V
PH
V+
t
V
PM
V
PL
0
Address 1
Address 2
Address n ( d 31)
Figure 8. Pulse sequence to select addresses
Falling edge of final B
OP
address digit
V
PH
V+
t
V
PM
V
PL
0
Encode Lock Bit
Enable
Address
Blow
32 pulses
Figure 9. Pulse sequence to encode lock bit
Lock Bit Programming. After the desired B
OP
calibration value
is programmed, and all of the corresponding bit eld-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bit eld address 32) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bit elds, as shown in gure 9.
Address Selection. After addressing mode is enabled, the
target bit eld address, is indicated by a series of V
PM
pulses, as
shown in gure 8.
Figure 7. Addressing mode enable pulse sequence
V
PH
V+
t
V
PM
V
PL
0
Enabling Addressing Mode. The rst segment of code is a
keying sequence used to enable the bit eld addressing mode. As
shown in gure 7, this segment consists of one short V
PH
pulse,
one V
PM
pulse, and one short V
PH
pulse, with no supply inter-
ruptions. This sequence is designed to prevent the device from
being programmed accidentally, such as by noise on the supply
line.
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