参数资料
| 型号： | A1240A-PG132C |
| 厂商： | Microsemi SoC |
| 文件页数： | 20/54页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 4K GATES 132-CPGA COM |
| 标准包装： | 21 |
| 系列： | ACT™ 2 |
| LAB/CLB数： | 684 |
| 输入/输出数： | 104 |
| 门数： | 4000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 通孔 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 132-BCPGA |
| 供应商设备封装： | 132-CPGA（34.54x34.54） |
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ACT 2 Family FPGAs
R e visio n 8
2 - 21
Pin Descriptions
CLKA
Clock A (Input)
TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
CLKB
Clock B (Input)
TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is
High. This pin functions as an I/O when the MODE pin is Low.
GND
Ground
Low supply voltage.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are
compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven Low
by the ALS software.
MODE
Mode (Input)
The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is
High, the special functions are active. When the MODE pin is Low, the pins function as I/Os. To provide
Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the
MODE pin can be pulled High when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA
Probe A (Output)
The Probe A pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic
output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is active when the MODE pin is High. This pin functions as an
I/O when the MODE pin is Low.
PRB
Probe B (Output)
The Probe B pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic
output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is active when the MODE pin is High. This pin functions as an
I/O when the MODE pin is Low.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is High.
This pin functions as an I/O when the MODE pin is Low.
SDO
Serial Data Output (Output)
Serial data output for diagnostic probe. SDO is active when the MODE pin is High. This pin functions as
an I/O when the MODE pin is Low.
VCC
5.0 V Supply Voltage
High supply voltage.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A1240A-PG132M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 2 Family 4K Gates 684 Cells 90MHz 1.0um Technology 5V 132-Pin CPGA |
| A1240A-PG160B | 制造商:MICROSEMI 制造商全称:Microsemi Corporation 功能描述:ACT 2 Family FPGAs |
| A1240A-PG160C | 制造商:MICROSEMI 制造商全称:Microsemi Corporation 功能描述:ACT 2 Family FPGAs |
| A1240A-PG160I | 制造商:MICROSEMI 制造商全称:Microsemi Corporation 功能描述:ACT 2 Family FPGAs |
| A1240A-PG160M | 制造商:MICROSEMI 制造商全称:Microsemi Corporation 功能描述:ACT 2 Family FPGAs |
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