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参数资料
| 型号： | A1280A-1CQ172CX79 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, CQFP172 |
| 封装： | CERAMIC, CQFP-172 |
| 文件页数： | 14/54页 |
| 文件大小： | 333K |
| 代理商： | A1280A-1CQ172CX79 |
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RadTolerant FPGAs
v3.1
1-17
RT1020, A1020B Timing Characteristics
Table 1-10 RT1020, A1020B Logic and Input Modules
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
Std Speed
Parameter
Description
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
Single Module
3.6
ns
tPD2
Dual Module Macros
8.4
ns
tCO
Sequential Clock to Q
3.6
ns
tGO
Latch G to Q
3.6
ns
tRS
Flip-Flop (Latch) Reset to Q
3.6
ns
Logic Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
1.1
ns
tRD2
FO=2 Routing Delay
1.8
ns
tRD3
FO=3 Routing Delay
2.6
ns
tRD4
FO=4 Routing Delay
3.9
ns
tRD8
FO=8 Routing Delay
8.1
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Setup
6.9
ns
tHD
3
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
6.9
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
8.4
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
8.4
ns
tA
Flip-Flop Clock Input Period
17.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency (FO = 128)
55
MHz
Input Module Propagation Delays
tINYH
Pad to Y High
3.9
ns
tINYL
Pad to Y Low
3.9
ns
Input Module Predicted Routing Delays1, 3
tIRD1
FO=1 Routing Delay
1.1
ns
tIRD2
FO=2 Routing Delay
1.8
ns
tIRD3
FO=3 Routing Delay
2.6
ns
tIRD4
FO=4 Routing Delay
3.9
ns
tIRD8
FO=8 Routing Delay
8.1
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
2. Setup times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. Optimization techniques may further reduce delays by 0 to 4ns.
4. The hold time for the DFME1A macro may be greater than 0ns. Use the Designer software 3.0 (or later) Timer to check the hold
time for this macro.
相关PDF资料 |
PDF描述 |
|---|---|
| A1280A-CQ172CX79 | FPGA, CQFP172 |
| A1280A-1CQG172B | FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172 |
| A1280A-1CQG172M | FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172 |
| A1280A-CQG172B | FPGA, 1232 CLBS, 8000 GATES, 41 MHz, CQFP172 |
| A1280A-CQG172M | FPGA, 1232 CLBS, 8000 GATES, 41 MHz, CQFP172 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1280A-1CQ172E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| A1280A-1CQ172M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 2 8K GATES 1232 CELLS 90MHZ 1.0UM 5V 172CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 140 I/O 172CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 8K GATES 172-CQFP MIL |
| A1280A-1CQ176B | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ACT2 Family FPGAs |
| A1280A-1CQ176C | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ACT2 Family FPGAs |
| A1280A-1CQ176I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ACT2 Family FPGAs |
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