- 您现在的位置：买卖IC网 > PDF目录294782 > A1280A-CQ172CX79 FPGA, CQFP172 PDF资料下载
参数资料
| 型号： | A1280A-CQ172CX79 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, CQFP172 |
| 封装： | CERAMIC, CQFP-172 |
| 文件页数： | 54/54页 |
| 文件大小： | 333K |
| 代理商： | A1280A-CQ172CX79 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页当前第54页
RadTolerant FPGAs
v3.1
1-5
output track is dedicated to the output of a particular
module. Long segments are uncommitted and can be
assigned during routing. Each output segment spans
four channels (two above and two below), except near
the top and bottom of the array where edge effects
occur. Long vertical tracks contain either one or two
segments. An example of vertical routing tracks and
segments is shown in Figure 1-5.
Antifuse Structures
An antifuse is a "normally open" structure as opposed to
the normally closed fuse structure used in PROMs
(programmable read-only memory) or PALs (programmed
array logic). The use of antifuses to implement a PLD
(programmable logic device) results in highly testable
structures, as well as efficient programming algorithms.
The structure is highly testable because there are no pre-
existing connections, enabling temporary connections to
be
made
using
pass
transistors.
These
temporary
connections can isolate individual antifuses to be
programmed, and also isolate individual circuit structures
to be tested. This can be done both before and after
programming. For example, all metal tracks can be tested
for continuity and shorts between adjacent tracks, and
the functionality of all logic modules can be verified.
Figure 1-5 Routing Structure
Vertical Routing Tracks
Segmented
Horizontal
Routing
Tracks
Logic
Modules
Antifuses
Table 1-1 Actel MIL-STD-883 Product Flow
Step
Screen
883 Method
883 - Class B
Requirement
1.
Internal Visual
2010, Test Condition B
100%
2.
Temperature Cycling
1010, Test Condition C
100%
3.
Constant Acceleration
2001, Test Condition D or E, Y1, Orientation Only
100%
4.
Seal
a. Fine
b. Gross
1014
100%
5.
Visual Inspection
2009
100%
6.
Pre-Burn-In Electrical Parameters
In accordance with applicable Actel device specification
100%
7.
Burn-in Test
1015, Condition D, 160 hours @ 125°C or 80 hours @ 150°C
100%
8.
Interim (Post-Burn-In) Electrical
Parameters
In accordance with applicable Actel device specification
100%
9.
Percent Defective Allowable
5%
All Lots
10.
Final Electrical Test
a. Static Tests
(1) 25°C (Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2, 3, Table I)
b. Functional Tests
(1) 25°C (Subgroup 7, Table I)
(2) –55°C and +125°C
(Subgroups 8A and 8B, Table I)
c. Switching Tests at 25°C
(Subgroup 9, Table I)
In accordance with applicable Actel device specification, which
includes a, b, and c:
5005
100%
11.
External Visual
2009
100%
Note: When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method
2018 must be waived.
相关PDF资料 |
PDF描述 |
|---|---|
| A1280A-1CQG172B | FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172 |
| A1280A-1CQG172M | FPGA, 1232 CLBS, 8000 GATES, 60 MHz, CQFP172 |
| A1280A-CQG172B | FPGA, 1232 CLBS, 8000 GATES, 41 MHz, CQFP172 |
| A1280A-CQG172M | FPGA, 1232 CLBS, 8000 GATES, 41 MHz, CQFP172 |
| A1020B-CQ84C | FPGA, 547 CLBS, 2000 GATES, 37 MHz, CQFP84 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1280A-CQ172E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| A1280A-CQ172M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 2 Family 8K Gates 1232 Cells 75MHz 1.0um (CMOS) Technology 5V 172-Pin CQFP 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 2 8K GATES 1232 CELLS 75MHZ 1.0UM 5V 172CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 8K GATES 172-CQFP MIL |
| A1280A-CQ176B | 制造商:MICROSEMI 制造商全称:Microsemi Corporation 功能描述:ACT 2 Family FPGAs |
| A1280A-CQ176C | 制造商:MICROSEMI 制造商全称:Microsemi Corporation 功能描述:ACT 2 Family FPGAs |
| A1280A-CQ176I | 制造商:MICROSEMI 制造商全称:Microsemi Corporation 功能描述:ACT 2 Family FPGAs |
发布紧急采购，3分钟左右您将得到回复。