参数资料
型号: A1321LLHLT-T
厂商: Allegro Microsystems Inc
文件页数: 11/13页
文件大小: 482K
描述: IC SENSOR HALL EFFECT SOT23W
产品培训模块: Current Sensor
标准包装: 1
传感范围: 4.75mV/G ~ 5.25mV/G
类型: 线性 - 比率型
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 8mA
电流 - 输出(最大): 10mA
输出类型: 数字式,开漏极
特点: 高灵敏度
工作温度: -40°C ~ 150°C
封装/外壳: SOT-23W
供应商设备封装: SOT-23W
包装: 标准包装
其它名称: 620-1023-6
Ratiometric Linear Hall Effect Sensor ICs
for High-Temperature Operation
A1321, A1322,
and A1323 
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power Derating
The device must be operated below the maximum junction
temperature of the device, T
J(max)
. Under certain combinations of
peak conditions, reliable operation may require derating sup-
plied power or improving the heat dissipation properties of the
application. This section presents a procedure for correlating
factors affecting operating T
J
. (Thermal data is also available on
the Allegro MicroSystems Web site.)
The Package Thermal Resistance, R
qJA
, is a  gure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, R
qJC
, is
relatively small component of R
qJA
. Ambient air temperature,
T
A
, and air motion are signi cant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at P
D
.
  P
D
= V
IN
 
?/DIV>
 I
IN
(1)
    DT = P
D
 
?/DIV>
 R
qJA
  (2)
    T
J
 = T
A
 + 擳     (3)
For example, given common conditions such as: T
A
= 25癈,
V
CC
= 12 V, I
CC
= 4 mA, and R
qJA
 = 140 癈/W, then:
    P
D
= V
CC
 
?/DIV>
 I
CC
= 12 V
?/DIV>
 4 mA = 48 mW
   DT = P
D
 
?/DIV>
 R
qJA
 = 48 mW
?/DIV>
 140 癈/W = 7癈
    T
J
 = T
A
 + DT = 25癈 + 7癈 = 32癈
A worst-case estimate, P
D(max)
, represents the maximum allow-
able power level (V
CC(max)
, I
CC(max)
), without exceeding T
J(max)
,
at a selected R
qJA
 and T
A
.
Example: Reliability for V
CC
 at T
A
=
 
150癈, package UA, using
minimum-K PCB.
Observe the worst-case ratings for the device, speci cally:
R
qJA
=
 
165癈/W, T
J(max)
=
 
165癈, V
CC(max)
=
 
5.5 V, and
I
CC(max)
=
 
8
 
mA.
Calculate the maximum allowable power level, P
D(max)
. First,
invert equation 3:
  DT
max
 = T
J(max)
  T
A
 = 165
 
 

 
150
 
癈 = 15
 
This provides the allowable increase to T
J
 resulting from internal
power dissipation. Then, invert equation 2:
  P
D(max)
= DT
max
 ?R
qJA
= 15癈 ?165 癈/W = 91 mW
Finally, invert equation 1 with respect to voltage:
  V
CC(est)
 = P
D(max)
? I
CC(max)
 = 91 mW ?8 mA = 11.4 V
The result indicates that, at T
A
, the application and device can
dissipate adequate amounts of heat at voltages dV
CC(est)
.
Compare V
CC(est)
 to V
CC(max)
. If V
CC(est)
 d V
CC(max)
, then reli-
able operation between V
CC(est)
 and V
CC(max)
 requires enhanced
R
qJA
. If V
CC(est)
 e V
CC(max)
, then operation between V
CC(est)
 and
V
CC(max)
 is reliable under these conditions.
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