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| 型号： | A1415A-2PLG84I |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 200 CLBS, 1500 GATES, PQCC84 |
| 封装： | PLASTIC, MS-007-AE, LCC-84 |
| 文件页数： | 68/68页 |
| 文件大小： | 489K |
| 代理商： | A1415A-2PLG84I |
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1-183
Accelerator Series FPGAs – ACT 3 Family
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer
connects to an associated I/O module with four signals: OE
(Output Enable), IE (Input Enable), DataOut, and DataIn.
Certain special signals used only during programming and
test also connect to the pad drivers: OUTEN (global output
enable), INEN (global input enable), and SLEW (individual
slew selection). See Figure 5.
Special I/Os
The special I/Os are of two types: temporary and permanent.
Temporary special I/Os are used during programming and
testing. They function as normal I/Os when the MODE pin is
inactive. Permanent special I/Os are user programmed as
either normal I/Os or special I/Os. Their function does not
change once the device has been programmed. The
permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input
buffer (HCLK), the hard-wired I/O clock input buffer
(IOCLK), and the hard-wired I/O register preset/clear input
buffer (IOPCL). Their function is determined by the I/O
macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two
high-performance dedicated clock networks and two general
purpose routed networks. The high-performance networks
function up to 200 MHz, while the general purpose routed
networks function up to 150 MHz.
Dedicated Clocks
Dedicated clock networks support high performance by
providing
sub-nanosecond
skew
and
guaranteed
performance.
Dedicated
clock
networks
contain
no
programming elements in the path from the I/O Pad Driver to
the input of S-modules or I/O modules. There are two
dedicated clock networks: one for the array registers (HCLK),
and one for the I/O registers (IOCLK). The clock networks
are accessed by special I/Os.
Figure 4 Functional Diagram for I/O Module
D
DATAOUT
D
Q
CLR/PRE
DATAIN
IOCLK
IOPCL
Y
D
Q
CLR/PRE
ODE
MUX
1
0
MUX
1
0
MUX
0
1
MUX
3
0
1
2
S1
S0
相关PDF资料 |
PDF描述 |
|---|---|
| A1415A-2PQG100C | FPGA, 200 CLBS, 1500 GATES, 200 MHz, PQFP100 |
| A1415A-2PQG100I | FPGA, 200 CLBS, 1500 GATES, PQFP100 |
| A1415A-2VQG100C | FPGA, 200 CLBS, 1500 GATES, 200 MHz, PQFP100 |
| A1415A-2VQG100I | FPGA, 200 CLBS, 1500 GATES, PQFP100 |
| A1415A-3PLG84C | FPGA, 200 CLBS, 1500 GATES, 250 MHz, PQCC84 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1415A-2PQ100C | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 100PQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 100PQFP - Trays |
| A1415A-2PQ100I | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 100PQFP - Trays |
| A1415A-2PQG100C | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 100PQFP - Trays |
| A1415A-2PQG100I | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 100PQFP - Trays |
| A1415A-2VQ100C | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 100VQFP - Trays |
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