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参数资料
型号： A1415A-VQG100I
厂商： Microsemi SoC
文件页数： 1/90页
文件大小： 0K
描述： IC FPGA 1500 GATES 100-VQFP
标准包装： 90
系列： ACT™ 3
LAB/CLB数： 200
输入/输出数： 80
门数： 1500
电源电压： 4.5 V ~ 5.5 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 100-TQFP
供应商设备封装： 100-VQFP（14x14）
January 2012
I
2012 Microsemi Corporation
Accelerator Series FPGAs – ACT 3 Family
Features
Up to 10,000 Gate Array Equivalent Gates (up to 25,000
equivalent PLD Gates)
Highly Predictable Performance with 100% Automatic Place-
and-Route
As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)
Up to 186 MHz On-Chip Performance (–1 Speed Grade)
Up to 228 User-Programmable I/O Pins
Four Fast, Low-Skew Clock Networks
More than 500 Macro Functions
Replaces up to Twenty 32 Macro-Cell CPLDs
Replaces up to One Hundred 20-Pin PAL Packages
Up to 1,153 Dedicated Flip-Flops
VQFP, TQFP, BGA, and PQFP Packages
Nonvolatile, User Programmable
Fully Tested Prior to Shipment
5.0 V and 3.3 V Versions
Optimized for Logic Synthesis Methodologies
Low Power CMOS Technology
Table 1 ACT 3 Family Product Information
Device
A1415
A1425
A1440
A1460
A14100
Capacity
Gate Array Equivalent Gates
1,500
2,500
4,000
6,000
10,000
PLD Equivalent Gates
3,750
6,250
10,000
15,000
25,000
TTL Equivalent Package (40 gates)
40
60
100
150
250
20-Pin PAL Equivalent Packages (100 gates)
15
25
40
60
100
Logic Modules
200
310
564
848
1,377
S-Module
104
160
288
432
697
C-Module
96
150
276
416
680
Dedicated Flip-Flops1
264
360
568
768
1,153
User I/Os (maximum)
80
100
140
168
228
Maximum Performance2 (worst-case commercial, –1 speed grade)
Chip-to-Chip3 (MHz)
80
78
76
Accumulators (16-bit, MHz)
47
Loadable Counter (16-bit, MHz)
82
78
Prescaled Loadable Counters (16-bit, MHz)
186
150
Datapath, Shift Registers (MHz)
186
150
Clock-to-Output (pad-to-pad, ns)
9.0
9.5
10.0
10.5
Packages4 (by pin count)
CPGA
PLCC
PQFP
RQFP
VQFP
TQFP
BGA
CQFP
PG1005
PL84
PQ100
–
VQ100
–
PG1335
PL84
PQ100, PQ160
–
VQ100
–
CQ132
PG1755
PL84
PQ160
–
VQ100
TQ176
–
PG207
–
PQ160, PQ208
–
TQ176
BG2255
CQ196
PG257
–
RQ208
–
BG313
CQ256
Notes:
1. One flip-flop per S0Module, two flip-flops per I/O Module.
2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.
3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the "System Performance Model" on page 1-1 and
Table 1-1 on page 1-2.
4. See the "Product Plan" table on page III for package availability.
5. Discontinued device and package combination.
6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product
Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:
PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004
Revision 3
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