参数资料
型号: A1425A-VQ100C
厂商: Microsemi SoC
文件页数: 89/90页
文件大小: 0K
描述: IC FPGA 2500 GATES 100-VQFP
产品变化通告: A1425A Family Discontinuation 23/Jan/2012
标准包装: 90
系列: ACT™ 3
LAB/CLB数: 310
输入/输出数: 83
门数: 2500
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 100-TQFP
供应商设备封装: 100-VQFP(14x14)
R e visio n 3
2 -1
2 – Detailed Specifications
This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of
FPGA devices. A generic description of the family will be presented first, followed by a detailed
description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The
on-chip circuitry required to program the devices is not covered.
Topology
The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad
Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is
similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array
itself consists of alternating rows of modules and channels. The logic modules and channels are in the
center of the array; the I/O modules are located along the array periphery. A simplified floor plan is
depicted in Figure 2-1.
Figure 2-1
Generalized Floor Plan of ACT 3 Device
IO
C
SC
S
IO
C
SC
S
IO
C
SC
S
IO
C
BIO IO
IO
BIN S
C
S
IO
BIN S
C
S
IO
BIN S
C
S
IO
CLKM
IO
BIN S
C
IO
CS
SC
S
IO
C
An Array with
n rows and m columns
Top I/Os
Bottom I/Os
Left I/Os
Right I/Os
Rows
n+1
n
n–1
2
1
0
Channels
n+1
n
n–1
2
1
0
n+2
0
1
2
3
4
5
c–1
c
c+1
m m+1 m+2 m+3
Columns
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