参数资料
| 型号： | A1460A-1TQ176I |
| 厂商： | Microsemi SoC |
| 文件页数： | 46/90页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 6K GATES 176-TQFP |
| 标准包装： | 40 |
| 系列： | ACT™ 3 |
| LAB/CLB数： | 848 |
| 输入/输出数： | 151 |
| 门数： | 6000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 176-LQFP |
| 供应商设备封装： | 176-TQFP（24x24） |
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Detailed Specifications
2- 42
R e visio n 3
Pin Descriptions
CLKA
Clock A (Input)
Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules.
This pin can also be used as an I/O.
CLKB
Clock B (Input)
Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules.
This pin can also be used as an I/O.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired)
Array Clock (Input)
Clock input for sequential modules. This input is directly wired to each S-Module and offers clock speeds
independent of the number of S-Modules being driven. This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are
compatible with standard TTL and CMOS specifications. Unused I/O pins are tristated by the Designer
Series software.
IOCLK
Dedicated (Hard-wired)
I/O Clock (Input)
Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds
independent of the number of I/O modules being driven. This pin can also be used as an I/O.
IOPCL
Dedicated (Hard-wired)
I/O Preset/Clear (Input)
Input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O
registers. This pin functions as an I/O when no I/O preset or clear macros are used.
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is
HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide
Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the
MODE pin can be pulled high when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA
Probe A (Output)
The Probe A pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic
output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as
an I/O when the MODE pin is LOW.
PRB
Probe B (Output)
The Probe B pin is used to output data from any user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic
output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as
an I/O when the MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW.
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| A1460A-1TQG176C | 功能描述:IC FPGA 6K GATES 176-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A1460A-1TQG176I | 功能描述:IC FPGA 6K GATES 176-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
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