参数资料
| 型号： | A1460A-TQ176I |
| 厂商： | Microsemi SoC |
| 文件页数： | 5/90页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 6K GATES 176-TQFP |
| 标准包装： | 40 |
| 系列： | ACT™ 3 |
| LAB/CLB数： | 848 |
| 输入/输出数： | 151 |
| 门数： | 6000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 176-LQFP |
| 供应商设备封装： | 176-TQFP（24x24） |
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Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -5
Dedicated Clocks
Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed
performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad
Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the
array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by
special I/Os.
The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock
module (CLKMOD) that selects the source of the clock signal and may be driven as follows (Figure 2-6):
Externally from the CLKA pad
Externally from the CLKB pad
Internally from the CLKINA input
Internally from the CLKINB input
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel. The function of the clock module is determined
by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of
the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally
generated clock signal to a clock network. Since both clock networks are identical, the user does not care
whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like
resets, output enables, or data enables. This saves logic modules and results in performance increases
in some cases.
Routing Structure
The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O
modules. These routing tracks are metal interconnects that may either be of continuous length or broken
into segments. Segments can be joined together at the ends using antifuses to increase their lengths up
to the full length of the track.
Figure 2-6
Clock Networks
CLKB
CLKA
FROM
PADS
CLOCK
DRIVERS
CLKMOD
CLKINB
CLKINA
S0
S1
INTERNAL
SIGNAL
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
CLOCK TRACKS
相关PDF资料 |
PDF描述 |
|---|---|
| A1460A-TQG176I | IC FPGA 6K GATES 176-TQFP |
| FMM22DSEF-S13 | CONN EDGECARD 44POS .156 EXTEND |
| FMM22DRKF-S13 | CONN EDGECARD 44POS .156 EXTEND |
| EP1S25B672C7 | IC STRATIX FPGA 25K LE 672-BGA |
| APA750-FG676I | IC FPGA PROASIC+ 750K 676-FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1460A-TQG176C | 功能描述:IC FPGA 6K GATES 176-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A1460A-TQG176I | 功能描述:IC FPGA 6K GATES 176-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A1460B-1BG225C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| A1460B-1PQ160C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| A1460B-1PQ160I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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