参数资料
型号: A14V60A-PQ160C
厂商: Microsemi SoC
文件页数: 3/90页
文件大小: 0K
描述: IC FPGA 6K GATES 3.3V 160-PQFP
标准包装: 24
系列: ACT™ 3
LAB/CLB数: 848
输入/输出数: 131
门数: 6000
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 160-BQFP
供应商设备封装: 160-PQFP(28x28)
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -3
The S-module contains a full implementation of the C-module plus a clearable sequential element that
can either implement a latch or flip-flop function. The S-module can therefore implement any function
implemented by the C-module. This allows complex combinatorial-sequential functions to be
implemented with no delay penalty. The Designer Series Development System will automatically
combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic
module and eliminating a module delay.
The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected
to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional
descriptions are shown in Figure 2-2 and Figure 2-3 on page 2-2. The clock selection is determined by a
multiplexer select at the clock input to the S-module.
I/Os
I/O Modules
I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in
the array and access the routing channels in a similar fashion to logic modules. The I/O module
schematic is shown in Figure 4. The signals DataIn and DataOut connect to the I/O pad driver.
Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock
(IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data
enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous
preset/clear input is driven by the dedicated preset/clear network (IOPCL). Either preset or clear can be
selected individually on an I/O module by I/O module basis.
Figure 2-4
Functional Diagram for I/O Module
D
DATAOUT
D
Q
CLR/PRE
DATAIN
IOCLK
IOPCL
Y
D
Q
CLR/PRE
ODE
MUX
1
0
MUX
1
0
MUX
0
1
MUX
3
0
1
2
S1
S0
相关PDF资料
PDF描述
A14V60A-PQG160C IC FPGA 6K GATES 3.3V 160-PQFP
ACC43DRAS CONN EDGECARD 86POS .100 R/A DIP
ACM44DSAS CONN EDGECARD 88POS R/A .156 SLD
EP2SGX30DF780C4N IC STRATIX II GX 30K 780-FBGA
RSC60DRTN-S734 CONN EDGECARD 120PS DIP .100 SLD
相关代理商/技术参数
参数描述
A14V60A-PQ208C 功能描述:IC FPGA 6K GATES 3.3V 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP,带拉杆 供应商设备封装:352-CQFP(75x75)
A14V60A-PQG160C 功能描述:IC FPGA 6K GATES 3.3V 160-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP,带拉杆 供应商设备封装:352-CQFP(75x75)
A14V60A-PQG208C 功能描述:IC FPGA 6K GATES 3.3V 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP,带拉杆 供应商设备封装:352-CQFP(75x75)
A14V60A-TQ176C 功能描述:IC FPGA 6K GATES 3.3V 176-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP,带拉杆 供应商设备封装:352-CQFP(75x75)
A14V60A-TQG176C 功能描述:IC FPGA 6K GATES 3.3V 176-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP,带拉杆 供应商设备封装:352-CQFP(75x75)