A28F400BR-T/B
10
ADVANCE INFORMATION
2.1.2
TWO 8-KB PARAMETER BLOCKS
The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the byte-
rewrite functionality of EEPROMs can be emulated.
These techniques are detailed in Intel’s
AP-604,
Using Intel’s Boot Block Flash Memory Parameter
Blocks to Replace EEPROM
. Each boot block
component contains two parameter blocks of
8 Kbytes (8,192 bytes) each. The parameter blocks
are not write-protectable.
2.1.3
ONE 96-KB + THREE 128-KB MAIN
BLOCKS
After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each 4-Mbit
device contains one 96-Kbyte (98,304 byte) block
and three 128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more information.
3.0
PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical program and erase. The boot
block flash family utilizes a Command User
Interface (CUI) and automated algorithms to
simplify program and erase operations. The CUI
allows for 100% TTL-level control inputs, fixed
power supplies during erasure and programming,
and maximum EPROM compatibility.
When V
PP
< V
PPLK
, the device will only successfully
execute the following commands: Read Array,
Read Status Register, Clear Status Register and
intelligent identifier mode. The device provides
standard EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the CUI
or through the standard EPROM A
9
high voltage
access (V
ID
) for PROM programming equipment.
The same EPROM read, standby and output
disable functions are available when 5V or 12V is
applied to the V
PP
pin. In addition, 5V or 12V on
V
PP
allows program and erase of the device. All
functions associated with altering memory contents:
Program and Erase, Intelligent Identifier Read, and
Read Status are accessed via the CUI.
The purpose of the Write State Machine (WSM) is
to completely automate the program and erasure of
the device. The WSM will begin operation upon
receipt of a signal from the CUI and will report
status back through a Status Register. The CUI will
handle the WE# interface to the data and address
latches, as well as system software requests for
status while the WSM is in operation.
3FFFFH
30000H
20000H
10000H
04000H
03000H
02000H
00000H
28F400-B
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
28F400-T
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
3FFFFH
3E000H
3D000H
3C000H
30000H
20000H
10000H
00000H
0538-03
Figure 3. 28F400-T/B Memory Maps