参数资料
型号: A29040P-70
英文描述: IC-4M FLASH
中文描述: 集成电路分闪光
文件页数: 24/30页
文件大小: 290K
代理商: A29040P-70
A29040A Series
PRELIMINARY (December, 2002, Version 0.2)
24
AMIC Technology, Corp.
Timing Waveforms for Alternate
CE
Controlled Write Operation
Erase and Programming Performance
Parameter
Typ. (Note 1)
1
8
35
3.6
Max. (Note 2)
8
64
300
10.8
Unit
sec
sec
μ
s
sec
Comments
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time (Note 3)
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 5.0V VCC, 100,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. Under worst case conditions of 90
°
C, VCC = 4.5V (4.75V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only
then does the device set I/O
5
= 1. See the section on I/O
5
for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See
Table 4 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
Excludes 00h programming
prior to erasure (Note 4)
Excludes system-level
overhead (Note 5)
Addresses
WE
OE
CE
Data
555 for program
2AA for erase
PA
D
OUT
~
~
I/O
7
~
~
~
Data Polling
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O
7
= Complement of Data Input, D
OUT
= Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
PD for program
30 for sector erase
10 for chip erase
~
t
BUSY
t
WHWH1 or 2
t
AH
t
AS
t
WC
t
WH
t
GHEL
t
CP
t
WS
t
CPH
PA for program
SA for sector erase
555 for chip erase
A0 for program
55 for erase
t
RH
t
DS
t
DH
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