参数资料
型号: A29L400SERIES
英文描述: 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only. Boot Sector Flash Memory
中文描述: 为512k × 8位/ 256 × 16位的CMOS 3.0伏特只。引导扇区闪存
文件页数: 7/40页
文件大小: 387K
代理商: A29L400SERIES
A29L400 Series
PRELIMINARY (October, 2002, Version 0.2)
7
AMIC Technology, Inc.
Output Disable Mode
When the
OE
input is at V
IH
, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET
: Hardware Reset Pin
The
RESET
pin provides a hardware method of resetting
the device to reading array data. When the system drives
the
RESET
pin low for at least a period of t
RP
, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
RESET
pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
Current is reduced for the duration of the
RESET
pulse.
When
RESET
is held at VSS
±
0.3V, the device draws
CMOS standby current (I
CC4
). If
RESET
is held at V
IL
but
not within VSS
±
0.3V, the standby current will be greater.
The
RESET
pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If
RESET
is asserted during a program or erase operation,
the RY/
BY
pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time t
READY
(during
Embedded Algorithms). The system can thus monitor
RY/
BY
to determine whether the reset operation is
complete. If
RESET
is asserted when a program or erase
operation is not executing (RY/
BY
pin is “1”), the reset
operation is completed within a time of t
READY
(not during
Embedded Algorithms). The system can read data t
RH
after
the
RESET
pin return to V
IH
.
Refer to the AC Characteristics tables for
RESET
parameters and diagram.
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