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参数资料
| 型号： | A3932SEQTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MOSFET 3PH 32-PLCC |
| 标准包装： | 1 |
| 应用： | DC 电机控制器，无刷（BLDC），3 相 |
| 输出数： | 1 |
| 电源电压： | 18 V ~ 50 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-PLCC |
| 供应商设备封装： | 32-PLCC |
| 包装： | 剪切带 (CT) |
| 其它名称： | 620-1128-1 |
A3932
Three-Phase Power MOSFET Controller
Terminal Descriptions (cont’d)
FAULT — Open-drain output to indicate fault condition; FAULT
= 1 (external pull-up) for any of the following:
1 – invalid HALL input code,
2 – undervoltage condition detected at VREG.
3 – thermal shutdown, or
4 – motor lead (SA/SB/SC) shorted to ground.
Except for a short-to-ground fault that only turns off the
high-side drivers, faults will force a coast condition that turns off
all power MOSFETs. Only the short-to-ground fault is latched
but is cleared at each commutation. If the motor has stalled
due to a short-to-ground being detected, toggling the RESET
terminal or repeating a power-up sequence will clear the fault.
Typically pulled up to V LCAP (+5 V) with an external 5.1 k Ω
resistor.
MODE — A logic input to set current-decay method, internally
pulled up to V LCAP (+5 V). When in slow-decay mode (MODE
= 1), only the high-side MOSFET is switched off during a
PWM-off cycle. The fast-decay mode (MODE = 0) switches
both the high-side and low-side MOSFETs.
H1/H2/H3 — Hall-sensor inputs; internally pulled up to V LCAP
(+5 V). Con ? gured for 120° electrical spacing.
DIR — A logic input to reverse rotation, see Commutation Truth
Table. Internally pulled up to V LCAP (+5 V).
BRAKE — An active-low logic input for a braking function.
A BRAKE = 0 will turn on the low-side FETs and turn off the
high-side FETs. This will effectively short-circuit the BEMF in
the windings and brake the motor. The braking torque applied
will depend on the speed. Internally pulled up to V LCAP (+5 V).
RESET = 1 overrides BRAKE and will coast the motor.
SR — Synchronous recti ? cation input. An SR = 0 disables this
feature, forcing current decay through the body diodes of the
power MOSFETs. An SR = 1 will result in appropriate high-
and low-side gate outputs to switch in response to a PWM-off
command. Internally pulled up to V LCAP (+5 V). See also the
Input Logic table.
TACH — An open-drain digital output whose frequency is pro-
portional to speed of rotation. A pulse appears at every HALL
transition. Typically pulled up to V LCAP (+5 V) with an external
5.1 k Ω resistor.
PWM — Speed control input, internally pulled up to V LCAP
(+5 V). A PWM = 0 turns off selected drivers. A PWM = 1 will
turn on selected drivers as determined by H1/H2/H3 input logic.
Holding PWM = 1 allows speed/torque control solely by the
internal current-limit circuit with the REF analog voltage. See
also the Input Logic table .
RC — An analog input used to set the ? xed off time with an
external resistor (R T ) and capacitor (C T ). The t blank time is con-
trolled by the value of the external capacitor (see Applications
Information). See Application Information.
SENSE — An analog input to the current-limit comparator.
A voltage representing load current appears on this terminal dur-
ing on time, when it reaches REF voltage, the comparator trips
and load current decays for the ? xed off-time interval. Volt-
age transients seen at this terminal when the drivers turn on are
ignored for time t blank .
REF — An analog input to the current-limit comparator. Volt-
age applied here with respect to AGND sets the peak load cur-
rent.
I peak = V REF /R S .
VREG — A regulated 13 V output; supply for low-side gate
drive and bootstrap capacitor charge circuits. It is good practice
to connect a decoupling capacitor from this terminal to AGND,
as close to the device terminals as possible. This terminal should
be shorted to V BB for 12 V applications.
VBB — The A3932 supply voltage. It is good practice to con-
nect a decoupling capacitor from this terminal to AGND, as
close to the device terminals as possible.
LCAP — Connection for 0.1 μ F decoupling capacitor for the
internal 5 V reference. This terminal can source no more than
3 mA for the DEAD input, TACH and FAULT outputs.
DEAD — An analog input. A resistor between DEAD and
LCAP is selected to adjust the turn-off to turn-on time. This
delay is needed to prevent shoot-through in the external power
MOSFETs. See Applications Information for details on setting
dead time.
AGND — The low-level (analog) reference point.
PGND — The return for all low-side gate drivers. This should
be connected to the system power ground.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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| A3932SLD-T | 功能描述:IC CTLR MOSFET 3PH 38-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器，驱动器 系列:- 标准包装:1 系列:- 应用:直流电机驱动器，步进电机驱动器 评估套件:- 输出数:1 或 2 电流 - 输出:750mA 电压 - 负载:10 V ~ 40 V 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-BFSOP（0.295"，7.50mm 宽） 供应商设备封装:24-SOP 包装:Digi-Reel® 其它名称:MTS62C19A-HS105DKR |
| A3932SLDTR-T | 功能描述:IC PWR MOSF CTLR 3PHASE 38-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器，驱动器 系列:- 标准包装:1 系列:- 应用:步进电机驱动器，1-2 相，2 相 评估套件:- 输出数:1 电流 - 输出:800mA 电压 - 负载:10 V ~ 28 V 电源电压:4.75 V ~ 5.25 V 工作温度:-20°C ~ 90°C 安装类型:表面贴装 封装/外壳:28-SOP + 2 翼片裸露焊盘 供应商设备封装:28-HSOPHC（15.2x7.9） 包装:剪切带 (CT) 其它名称:869-1268-1 |
| A3932SLDTR-T-CUT | 制造商:Allegro MicroSystems LLC 功能描述: |
| A3933 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:THREE-PHASE POWER MOSFET CONTROLLER |
| A3933SEQ | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:THREE-PHASE POWER MOSFET CONTROLLER |
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