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| 型号： | A3938SEQTR |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 6/11页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MOSFET 3PH 32-PLCC |
| 标准包装： | 800 |
| 应用： | DC 电机控制器，无刷（BLDC），3 相 |
| 输出数： | 1 |
| 电源电压： | 18 V ~ 50 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-PLCC |
| 供应商设备封装： | 32-PLCC |
| 包装： | 带卷 (TR) |
A3938
Three-Phase Power MOSFET Controller
Pin Descriptions
RESET. A logic input that enables the device. Has internal
50 k Ω pull-up to LCAP. Setting RESET to 1 coasts or brakes
the motor, depending on the state of the BRKSEL pin. Set-
ting RESET to 0 enables the gate drive to follow commuta-
tion logic. Setting RESET to 1 overrides the BRAKE pin.
GLA/GLB/GLC. Low-side gate drive outputs for external
MOSFET drivers. External series gate resistors can be used
to control slew rate seen at the power driver gate, thereby
controlling the di / dt and dv / dt of Sx outputs.
SA/SB/SC. Directly connected to the motor terminals,
these pins sense the voltages switched across the load. The
pins are also connected to the negative side of the bootstrap
capacitors and the negative supply connections for the ? oat-
ing high-side drivers.
GHA/GHB/GHC. High-side gate drive outputs for
N-channel MOSFET drivers. External series gate resistors
can be used to control slew rate seen at the power driver
gate, thereby controlling the di / dt and dv / dt of Sx outputs.
CA/CB/CC. High-side connections for bootstrap capaci-
tors, providing positive supply for high-side gate drivers. The
bootstrap capacitors are charged to approximately VREG
when the output Sx terminals go low. When the outputs
swing high, the voltages on these pins rise with the outputs to
provide the boosted gate voltages needed for the N-channel
power MOSFETs.
MODE. Logic input to set current-decay mode. In response
to a PWM Off command, Slow Decay mode (MODE = 1)
switches off the high-side FET, and Fast Decay mode
(MODE = 0) switches off the high-side and low-side FETs.
Has an internal 50 k Ω pull-up to LCAP.
H1/H2/H3. Hall sensor inputs with internal, 50 k Ω pull-ups
to LCAP. Con ? gured for 120-degree electrical spacing.
DIR. Logic input to reverse rotation (see the table Commu-
tation Truth Table, on the next page). Has internal, 50 k Ω
pull-up to LCAP.
FAULT. Open-drain output to indicate fault condition. Will
be pulled high (usually by 5.1 k Ω external pull-up) for any of
the following fault conditions:
? Invalid Hall sensor input code (coasts the motor).
? Undervoltage condition detected at VREG (coasts or brakes
the motor depending on stored setting for BRKSEL).
? Thermal shutdown (coasts the motor).
? Motor lead (SA/SB/SC) connected to ground (turns off
only the high-side power MOSFETs).
Only the “short-to-ground” fault is latched, but it is cleared
at each commutation. If the motor has stalled due to a short-
to-ground being detected, toggling the RESET pin or repeat-
ing a power-up sequence clears the fault.
BRAKE. Logic input for braking function. Setting BRAKE
to 1 turns on low-side MOSFETs, and turns off the high-side
MOSFETs. This effectively shorts the BEMF in the windings
and brakes the motor. Internal 50 k Ω pull-up to LCAP. Set-
ting RESET to 1 overrides this BRAKE pin. See also BRKSEL.
BRKCAP. This pin is for connection of the reservoir
capacitor used to provide the positive power supply for the
sink drive outputs for a power-down condition. This allows
predictable braking, if desired. Using a 4.7 ? F capacitor will
provide 6.5 V gate drive for 300 ms. If the power-down brak-
ing option is not needed (i.e., BRKSEL = 0), then this pin
should be tied to VREG.
BRKSEL . Logic input to enable/disable braking upon
power-down condition or RESET = 1. Internal 50 k Ω pull-up
to LCAP. Setting BRKSEL to 0 enables Coast mode. Setting
BRKSEL to 1 enables Brake mode.
PWM. Speed control input. Setting PWM to 1 turns on
MOSFETs selected by Hall input logic. Setting PWM to 0
turns off the selected MOSFETs. Keep the PWM input held
high to utilize internal current control circuitry. Internal
50 k Ω pull-up to LCAP.
RC. Analog input. Connection for R T and C T to set the
? xed off-time. C T also sets the BLANK time (see the section
Application Information). It is recommended that the ? xed
off-time should not be less than 10 μ s. The resistor should be
in the range between 10 k Ω and 500 k Ω .
VREG. Regulated 13 V supply for the low-side gate drive
and the bootstrap capacitor charge circuit. As a regulator, use
a 10 μ F decoupling/storage capacitor (ESR < 1 Ω ) from this
pin to AGND, as close to the device pins as possible.
Note: For 12 V applications, the VREG pin should be
shorted to VBB.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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