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参数资料
| 型号： | A3940KLWTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 6/13页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MOSFET FULL 28-SOIC |
| 标准包装： | 1,000 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 225ns |
| 电流 - 峰： | 700mA |
| 配置数： | 1 |
| 输出数： | 4 |
| 电源电压： | 7 V ~ 40 V |
| 工作温度： | -40°C ~ 135°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
3940
FULL-BRIDGE POWER
MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS: unless otherwise noted at T A = -40°C to +135°C, T J = -40°C to +150°C,
V IN ≤ V BB = 7 V to 40 V, C p = 0.47 μF, C r = 1 μF, C REG5 = 0.1 μF, C REG13 = 10 μF, C BOOT = 0.1 μF, PWM = 22.5 kHz
square wave.
Characteristics
Symbol
Conditions
Min
Limits
Typ Max
Units
Control Logic
Logic Input Voltage
Logic Input Current
V IN(1)
V IN(1)
V IN(0)
I IN(1)
I IN(0)
I IN(0)
HIGH level input (Logic 1), except RESET.
HIGH level input (Logic 1) for RESET
LOW level input (Logic 0)
V IN = 2.0 V
V IN = 0.8 V, except RESET(0)
V IN = 0.8 V, RESET(0)
2.0
2.2
–
–
–
–
–
–
–
40
16
–
–
–
0.8
100
40
1.0
V
V
V
μA
μA
μA
Gate Drives, GHx, GLx ( internal SOURCE or upper switch stages)
Output High Voltage
V DSL(H)
GHx: I xU = -10 mA, V sx = 0
GLx: I xU = -10 mA, V lss = 0
V REG13 - 2.2
V REG13 - 0.2
–
–
V REG13
V REG13
V
V
Source Current (pulsed)
Source ON Resistance
Source Load Rise Time
I xU
r SDU(on)
t r
V SDU = 10 V, T J = 25°C
V SDU = 10 V, T J = 135°C
I xU = -150 mA, T J = 25°C
I xU = -150 mA, T J = 135°C
Measure V DSL , 20% to 80%, C L = 3300 pF
– 700
400 –
4.0 –
7.0 –
– 90
–
–
13
23
–
mA
mA
?
?
ns
Gate Drives, GHx, GLx ( internal SINK or lower switch stages)
Output Low Voltage
Sink Current (pulsed)
Sink ON Resistance
Sink Load Fall Time
V DSL(L)
I xL
r DSL(on)
t f
GHx: I xL = 10 mA, V sx = 0
GLx: I xL = 10 mA, V lss = 0
V DSL = 10 V, T J = 25°C
V DSL = 10 V, T J = 135°C
I xL = +150 mA, T J = 25°C
I xL = +150 mA, T J = 135°C
Measure V DSL , 80% to 20%, C L = 3300 pF
–
–
–
550
1.8
3.0
–
–
–
800
–
–
–
70
150
150
–
–
6.0
7.5
–
mV
mV
mA
mA
?
?
ns
Gate Drives, GHx, GLx (General)
Propagation Delay
Output Skew Time
Dead Time
(Shoot-Through Prevention)
Between GHx, GLx transitions
of same phase
t pd
t sk(o)
t dead
Logic input to unloaded GHx, GLx
Grouped by rising or falling edge
LONG = 0, R DEAD = 12.1 k ? (I DEAD = 167 μA)
LONG = 0, R DEAD = 499 k ? (I DEAD = 4 μA)
LONG = 1, R DEAD = 12.1 k ? (I DEAD = 167 μA)
LONG = 1, R DEAD = 499 k ? (I DEAD = 4 μA)
–
–
0.3
–
8.3
–
–
–
–
–
–
–
225
50
–
11.0
–
345
ns
ns
μs
μs
μs
μs
NOTES: Typical Data is for design information only.
Negative current is defined as coming out of (sourcing) the specified device terminal.
For GH X : V SDU = V CX – V GHX , V DSL = V GHX – V SX , V DSL(H) = V CX – V SDU – V SX .
For GL X : V SDU = V REG – V GLX , V DSL = V GLX – V LSS , V DSL(H) = V REG – V SDU – V LSS.
Continued next page …
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