参数资料
型号: A3946KLPTR
厂商: Allegro Microsystems Inc
文件页数: 7/14页
文件大小: 0K
描述: IC CTRLR MOSFET 16-TSSOP
标准包装: 4,000
应用: DC 电机控制器,无刷(BLDC),3 相
输出数: 1
电源电压: 7 V ~ 60 V
工作温度: -40°C ~ 135°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 16-TSSOP-EP
包装: 带卷 (TR)
A3946
Dead Time . The analog input pin DT sets the delay to turn
on the high- or low-side gate outputs. When instructed to
turn off, the gate outputs change after an short internal propa-
gation delay (90 ns typical). The dead time controls the time
between this turn-off and the turn-on of the appropriate gate.
The duration, t DEAD , can be adjusted within the range 350 ns
to 6000 ns using the following formula:
t DEAD = 50 + ( R DEAD ? 16.7 )
where t DEAD is in ns, and R DEAD is in Ω , and should be in the
range 5 k Ω < R DEAD < 100 k Ω .
Do not ground the DT pin. If the DT pin is left open, dead
time defaults to 12 μ s.
Control Logic . Two different methods of control are
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by short-
ing IN1 with IN2. If a very slow turn-on is required (greater
than 6 μ s), the two input pins can be hooked-up individually
to allow the dead times to be as long as needed.
Fault Response Table
Half-Bridge Power MOSFET Controller
The dead time circuit can be disabled by tying the DT pin
to VREF. This disables the turn-on delay and allows direct
control of each MOSFET gate via two control lines. This is
shown in the Control Logic table, on page 2.
Top-Off Charge Pump . An internal charge pump allows
100% duty cycle operation of the high-side MOSFET. This is
a low-current trickle charge pump, and is only operated after
a high-side has been signaled to turn on. A small amount of
bias current is drawn from the BOOT pin to operate the ? oat-
ing high-side circuit. The top-off charge pump simply pro-
vides enough drive to ensure that the gate voltage does not
droop due to this bias supply current. The charge required for
initial turn-on of the high-side gate must be supplied by boot-
strap capacitor charge cycles. This is described in the section
Application Information.
VREF . VREF is used for the internal logic circuitry and
is not intended as an external power supply. However,
the VREF pin can source up to 4 mA of current. A 0.1 μ F
capacitor is needed for decoupling.
No Fault
Fault Mode
RESET
1
~FAULT
1
VREG
ON
VREF
ON
GH 1
(IL)
GL 1
(IL)
BOOT Capacitor Undervoltage
2
1
0
ON
ON
0
(IL)
VREG Undervoltage
3
1
0
ON
ON
0
0
VREF Undervoltage
4
1
0
OFF
ON
0
0
Thermal Shutdown
3
1
0
ON
ON
(IL)
(IL)
Sleep
5
0
1
OFF
OFF
High Z
High Z
1
2
3
(IL) indicates that the state is determined by the input logic.
This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched.
These faults are latched. Clear by pulsing RESET = 0. Note that outputs become active as soon as VREG comes out of undervoltage, even
though ~FAULT = 0.
4
5
Unspeci ? ed VREF undervoltage threshold < 4 V.
During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to be-
come high impedance (High Z). Refer to the section Sleep Mode/Power Up .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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