参数资料
型号: A3950SEUTR-T
厂商: Allegro Microsystems Inc
文件页数: 1/12页
文件大小: 0K
描述: IC MOTOR DVR FULL BRIDGE 16-QFN
标准包装: 1
应用: PWM 电机驱动器
输出数: 1
电流 - 输出: ±2.8A
电源电压: 8 V ~ 36 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WSQFN 裸露焊盘
供应商设备封装: 16-QFN-EP(4x4)
包装: 标准包装
产品目录页面: 1140 (CN2011-ZH PDF)
其它名称: 620-1296-6
A3950
DMOS Full-Bridge Motor Driver
Features and Benefits
Description
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Low R DS(on) outputs
Overcurrent protection
Motor lead short-to-supply protection
Short-to-ground protection
Sleep function
Synchronous rectification
Diagnostic output
Internal undervoltage lockout (UVLO)
Crossover-current protection
Designed for PWM (pulse width modulated) control of DC
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a DC motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-to-
supply / short-to-ground, thermal shutdown with hysteresis,
Packages:
undervoltage monitoring of V BB and V CP , and crossover-current
protection.
The A3950 is supplied in a thin profile (<1.2 mm overall height)
Package LP, 16 pin TSSOP
with Exposed Thermal Pad
Package EU, 16 pin QFN
with Exposed Thermal Pad
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
Approximate Scale 1:1
Typical Application Diagrams
0.22 μ F
25 V
V BB
0.1 μ F
50 V
V BB
V DD
5 k Ω
PHASE
GND
SLEEP
ENABLE
A3950
EU Package
GND
CP2
CP1
OUTB
0.1 μ F
50 V
100 μ F
50 V
V DD
5 k Ω
NFAULT
MODE
PHASE
GND
SLEEP
ENABLE
OUTA
A3950
LP Package
NC
VREG
VCP
GND
CP2
CP1
OUTB
0.1 μ F
50 V
0.1 μ F
50 V
0.22 μ F
25 V
100 μ F
50 V
SENSE
VBB
0.1 μ F
50 V
0.1 μ F
50 V
A3950DS, Rev. 6
Package EU
Package LP
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