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| 型号： | A3950SLP-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRIVER PWM FULL 16-TSSO |
| 标准包装： | 96 |
| 应用： | PWM 电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±2.8A |
| 电源电压： | 8 V ~ 36 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 管件 |
| 其它名称： | 620-1064 |
A3950
DMOS Full-Bridge Motor Driver
Functional Description
Device Operation . The A3950 is designed to operate one DC
motor. The output drivers are all low R DS(on) N-channel DMOS
drivers that feature internal synchronous rectification to reduce
power dissipation. PHASE and ENABLE inputs allow two-wire
control with an additional MODE pin for the brake function. A
low current Sleep mode is provided to minimize power consump-
tion when the driver is disabled. In addition, the driver also has
built-in protection from short-to-ground, short-to-battery, and
shorted load events.
Logic Inputs. If logic inputs are pulled up to V DD , it is good
practice to use a high value pull-up resistor in order to limit cur-
rent to the logic inputs should an overvoltage event occur. Logic
inputs include: SLEEP, MODE, PHASE, and ENABLE. The
voltage on any logic input cannot exceed the specified maximum
of 7 V.
VREG . This supply voltage is used to run the sink-side DMOS
outputs. VREG is internally monitored and in the case of a fault
condition, the outputs of the device are disabled. The VREG pin
should be decoupled with a 0.22 μ F capacitor to ground.
Charge Pump . The charge pump is used to generate a sup-
ply above V BB to drive the source-side DMOS gates. A 0.1 μ F
ceramic monolithic capacitor should be connected between CP1
and CP2 for pumping purposes. A 0.1 μ F ceramic monolithic
capacitor should be connected between VCP and VBB to act as a
reservoir to run the high-side DMOS devices. The VCP voltage
level is internally monitored and, in the case of a fault condition,
the device are disabled until the fault condition is removed. At
power-on the UVLO circuit disables the drivers.
Sleep Mode . Control input SLEEP is used to minimize power
consumption when the A3950 is not in use. This disables much
of the internal circuitry, including the regulator and charge pump.
A logic low setting puts the device into Sleep mode, and a logic
high setting allows normal operation. After coming out of Sleep
mode, provide a 1 ms interval before applying PWM signals, to
allow the charge pump to stabilize.
MODE . Control input MODE is used to toggle between fast
decay mode and slow decay mode. A logic high puts the device in
slow decay mode. Synchronous rectification is always enabled.
Braking . The braking function is implemented by driving the
device in slow decay mode via the MODE setting and applying
an enable chop command. Because it is possible to drive current
in both directions through the DMOS switches, this configuration
effectively shorts out the motor generated BEMF as long as the
ENABLE chop mode is asserted. The maximum current can be
approximated by V BEMF /R L . Care should be taken to insure that
the maximum ratings of the device are not exceeded in worse
case braking situations: high speed and high-inertia loads.
Diagnostic Output . The NFAULT pin signals a problem with
the chip via an open drain output. A motor fault, undervoltage
condition, or T J > 160°C will drive the pin active low. This output
is not valid when SLEEP puts the device into minimum power
dissipation mode.
the outputs of the device are disabled.
TSD . Two die temperature monitors are integrated on the chip.
Shutdown . In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
Control Logic Table 1
As die temperature increases towards the maximum, a thermal
warning signal will be triggered at 160°C. This fault drives the
PHASE
1
0
X
1
0
X
ENABLE
1
1
0
0
0
X
Pin
MODE
X
X
1
0
0
X
SLEEP
1
1
1
1
1
0
OUTA
H
L
L
L
H
Z
OUTB
L
H
L
H
L
Z
Function
Forward
Reverse
Brake (slow decay)
Fast Decay Synchronous Rectification 2
Fast Decay Synchronous Rectification 2
Sleep Mode
1 X
indicates “don’t care,” Z indicates high impedance.
2 To
prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A3950SLP-T | 制造商:Allegro MicroSystems 功能描述:DMOS Driver |
| A3950SLPTR-T | 功能描述:IC MOTOR DVR FULL BRIDGE 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器，驱动器 系列:- 产品变化通告:ATA683(3,4)PLQW Obsolescence 09/Aug/2012 标准包装:1 系列:- 应用:DC 电机控制器，无刷（BLDC），3 相 评估套件:可供 输出数:1 电流 - 输出:100mA 电压 - 负载:5.25 V ~ 20 V 电源电压:5.25 V ~ 20 V 工作温度:-40°C ~ 150°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-VQFN（7x7） 包装:剪切带 (CT) 其它名称:ATA6833-PLQWCT |
| A3951 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:FULL-BRIDGE PWM MOTOR DRIVER |
| A3951SB | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:FULL-BRIDGE PWM MOTOR DRIVER |
| A3951SW | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:FULL-BRIDGE PWM MOTOR DRIVER |
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