参数资料
型号: A3950SLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 10/12页
文件大小: 0K
描述: IC MOTOR DVR FULL BRIDGE 16TSSOP
标准包装: 1
应用: PWM 电机驱动器
输出数: 1
电流 - 输出: ±2.8A
电源电压: 8 V ~ 36 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 16-TSSOP-EP
包装: 标准包装
产品目录页面: 1140 (CN2011-ZH PDF)
其它名称: 620-1297-6
A3950
SENSE Pin. A low value resistor can be placed between the
SENSE pin and ground for current sensing purposes. To mini-
mize ground-trace IR drops in sensing the output current level,
the current sensing resistor should have an independent ground
return to the star ground point. This trace should be as short as
possible. For low value sense resistors, the IR drops in the PCB
can be significant, and should be taken into account.
When selecting a value for the sense resistor be sure not to
exceed the maximum voltage on the SENSE pin of ±500 mV.
Ground . A star ground should be located as close to the A3950
as possible. The copper ground plane directly under the exposed
thermal pad makes a good location for the star ground point. The
exposed pad can be connected to ground for this purpose.
VBB
DMOS Full-Bridge Motor Driver
Layout. The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A3950 must be soldered directly onto the board. On the under-
side of the A3950 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
The load supply pin, VBB, should be decoupled with an elec-
trolytic capacitor (typically 100 μ F) in parallel with a ceramic
capacitor placed as close as possible to the device. The ceramic
capacitors between VCP and VBB, connected to VREG, and
between CP1 and CP2, should be as close to the pins of the
device as possible, in order to minimize lead inductance.
V BB
C1
C2
CVBB1
PHASE
C1
C2
GND
CVBB1
GND
U1
GND
SLEEP
A3950
EU Package
PAD
CP2
CP1
C3
OUTA
CVBB2
C3
OUTB
GND
ENABLE
OUTB
CVBB2
EU package shown
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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