参数资料
型号: A3953SLB-T
厂商: Allegro Microsystems Inc
文件页数: 2/12页
文件大小: 0K
描述: IC MOTOR DRIVER PWM FULL 16-SOIC
标准包装: 47
应用: PWM 电机驱动器
输出数: 1
电流 - 输出: ±1.3A
电压 - 负载: 3 V ~ 50 V
电源电压: 3 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
其它名称: 620-1066
A3953
Full-Bridge PWM Motor Driver
Features and Benefits
? ±1.3 A continuous output current
? 50 V output voltage rating
? 3 V to 5.5 V logic supply voltage
? Internal PWM current control
? Saturated sink drivers (below 1 A)
? Fast and slow current-decay modes
? Automotive capable
? Sleep (low current consumption) mode
? Internal transient-suppression diodes
? Internal thermal shutdown circuitry
? Crossover current and UVLO protection
Packages:
Description
Designed for bidirectional pulse width modulated (PWM)
current control of inductive loads, the A3953 is capable of
continuous output currents to ±1.3 A and operating voltages
to 50 V. Internal fixed off-time PWM current-control circuitry
can be used to regulate the maximum load current to a desired
value. The peak load current limit is set by the user ’s selection
of an input reference voltage and external sensing resistor. The
fixed off-time pulse duration is set by a user- selected external
RC timing network. Internal circuit protection includes thermal
shutdown with hysteresis, transient-suppression diodes, and
crossover current protection. Special power-up sequencing is
not required.
With the ENABLE input held low, the PHASE input controls
load current polarity by selecting the appropriate source and
sink driver pair. The MODE input determines whether the
PWM current-control circuitry operates in a slow current-decay
mode (only the selected source driver switching) or in a fast
Package B, 16-pin DIP
with exposed tabs
Not to scale
Package LB, 16-pin SOIC
with internally fused pins
current-decay mode (selected source and sink switching). A
user-selectable blanking window prevents false triggering of
the PWM current-control circuitry. With the ENABLE input
held high, all output drivers are disabled. A sleep mode is
provided to reduce power consumption.
Continued on the next page…
Functional Block Diagram
LOGIC
SUPPLY
6 V CC
9
10
15
16
SLEEP &
STANDBY MODES
MODE
PHASE
ENABLE
BRAKE
14
7
8
1
UVLO
& TSD
V BB
PWM LATCH
R
Q
11
SENSE
BLANKING
S
RS
GROUND
4
5
V CC
RC
3
+ –
2
12
13
REF
GROUND
RT
CT
V TH
Dwg. FP-036-2A
29319.8I
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