参数资料
型号: A3955SLBTR-T
厂商: Allegro Microsystems Inc
文件页数: 8/14页
文件大小: 0K
描述: IC MOTOR DRIVER PWM FULL 16-SOIC
标准包装: 1
应用: 步进电机驱动器
输出数: 1
电流 - 输出: ±1.5A
电压 - 负载: 4.5 V ~ 50 V
电源电压: 4.5 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 标准包装
产品目录页面: 1140 (CN2011-ZH PDF)
其它名称: 620-1134-6
A3955
Full-Bridge PWM Microstepping Motor Driver
Functional Description
Two A3955 full-bridge PWM microstepping motor drivers are
needed to drive the windings of a bipolar stepper motor. Internal
pulse width modulated (PWM) control circuitry regulates each
motor winding current. The peak motor current is set by the
value of an external current-sense resistor (R S ), a reference
voltage (V REF ), and the digital-to-analog converter (DAC) data
inputs (D 0 , D 1 , and D 2 ).
To improve motor performance, especially when using
sinusoidal current pro ? les necessary for microstepping, the
A3955 has three distinct current-decay modes: slow decay, fast
decay, and mixed decay.
PHASE Input. The PHASE input controls the direction of
current ? ow in the load (table 1). An internally generated dead
time of approximately 1 μ s prevents crossover currents that
could occur when switching the PHASE input.
DAC Data Inputs (D 0 , D 1 , D 2 ). A non-linear DAC is used
to digitally control the output current. The output of the DAC is
used to set the trip point of the current-sense comparator. Table 3
shows DAC output voltages for each input condition. When D 0 ,
D 1 , and D 2 are all logic low, all of the power output transistors
are turned off.
Internal PWM Current Control. Each motor driver
contains an internal ? xed off-time PWM current-control circuit
that limits the load current to a desired value (I TRIP ). Initially,
a diagonal pair of source and sink transistors are enabled and
current ? ows through the motor winding and R S ( ? gure 1). When
the voltage across the sense resistor equals the DAC output
voltage the current-sense comparator resets the PWM latch,
V
BB
which turns off the source drivers (slow-decay mode) or the sink
and source drivers (fast- or mixed-decay mode).
With the DATA input lines tied to V CC , the maximum value of
current limiting is set by the selection of R S and V REF with a
transconductance function approximated by:
I TRIP ≈ V REF / 3R S .
The actual peak load current (I PEAK ) will be slightly higher than
I TRIP due to internal logic and switching delays. The driver(s)
remain off for a time period determined by a user-selected
external resistor-capacitor combination (R T C T ). At the end of
the ? xed off-time, the driver(s) are re-enabled, allowing the load
current to increase to I TRIP again, maintaining an average load
current.
The DAC data input lines are used to provide up to eight levels
of output current. The internal 3-bit digital-to-analog converter
reduces the reference input to the current-sense comparator
in precise steps (the step reference current ratio or SRCR) to
provide half-step, quarter-step, or “microstepping” load-current
levels.
I TRIP ≈ SRCR x V REF /3R S
Slow Current-Decay Mode. When V PFD ≥ 3.5 V, the
device is in slow current-decay mode (the source drivers are
disabled when the load current reaches I TRIP ). During the ? xed
off-time, the load inductance causes the current to recirculate
through the motor winding, sink driver, ground clamp diode,
and sense resistor (see ? gure 1). Slow-decay mode produces
low ripple current for a given ? xed off-time (see ? gure 2).
Low ripple current is desirable because the average current
in the motor winding is more nearly equal to the desired
DRIVE CURRENT
I PEAK
SLOW (V PFD ≥ 3.5 V)
MIXED (1.1 V ≤ V PFD ≤ 3.1 V)
RECIRCULATION
(SLOW-DECAY MODE)
RECIRCULATION
(FAST-DECAY MODE)
PFD
t OFF
FAST (V PFD ≤ 0.8 V)
Dwg. WP-031-1
RS
Dwg. EP-006-15
Figure 1 — Load-Current Paths
Figure 2 — Current-Decay Waveforms
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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