参数资料
型号: A3959SLBTR
厂商: Allegro Microsystems Inc
文件页数: 6/12页
文件大小: 0K
描述: IC MOTOR DRIVER PWM FULL 24-SOIC
标准包装: 1,000
应用: PWM 电机驱动器
输出数: 1
电流 - 输出: ±3A
电压 - 负载: 9.5 V ~ 50 V
电源电压: 4.5 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
A3959
DMOS Full-Bridge PWM Motor Driver
FUNCTIONAL DESCRIPTION
V REG . This internally generated voltage is used to operate
the sink-side DMOS outputs. The V REG terminal should
be decoupled with a 0.22 μ F capacitor to ground. V REG is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump. The charge pump is used to generate a
EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high, slow
decay mode, both sink drivers are on with ENABLE low.
gate-supply voltage greater than V BB to drive the source-
side DMOS gates. A 0.22 μ F ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
EXT MODE
0
Decay
Fast
A 0.22 μ F ceramic capacitor should be connected between
CP and V BB to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
PHASE Logic. The PHASE input terminal determines if
the device is operating in the “forward” or “reverse” state.
PHASE OUT A OUT B
1 Slow
Current Regulation. Load current is regulated by an
internal ? xed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (R S ) and the
applied analog reference voltage (V REF ):
I TRIP = V REF /10R S
0
1
Low
High
High
Low
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
ENABLE Logic. The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.
? xed off-time period. The current path during recirculation
is determined by the con ? guration of slow/mixed/fast
current-decay mode via PFD1 and PFD2.
Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the R OSC
terminal to V DD . Typical value of 4 MHz is set with a
51 k Ω resistor. The allowable range of the resistor is from
ENABLE
Outputs
20 k Ω to 100 k Ω .
f OSC = 204 x 10 9 /R OSC .
0
1
Chopped
On
If R OSC is not pulled up to V DD , it must be shorted to
ground.
Fixed Off Time. The A3959 is set for a ? xed off time of
96 cycles of the internal oscillator, typically 24 μ s with a
4 MHz oscillator.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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A3959SLP-T 功能描述:IC MOTOR DRIVER PWM FULL 28TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器,驱动器 系列:- 标准包装:1 系列:- 应用:直流电机驱动器,步进电机驱动器 评估套件:- 输出数:1 或 2 电流 - 输出:750mA 电压 - 负载:10 V ~ 40 V 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-BFSOP(0.295",7.50mm 宽) 供应商设备封装:24-SOP 包装:Digi-Reel® 其它名称:MTS62C19A-HS105DKR
A3959SLP-T 制造商:Allegro MicroSystems 功能描述:Motor Driver IC
A3959SLPTR 功能描述:IC MOTOR DRIVER PWM FULL 28TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器,驱动器 系列:- 标准包装:1 系列:- 应用:直流电机驱动器,步进电机驱动器 评估套件:- 输出数:1 或 2 电流 - 输出:750mA 电压 - 负载:10 V ~ 40 V 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-BFSOP(0.295",7.50mm 宽) 供应商设备封装:24-SOP 包装:Digi-Reel® 其它名称:MTS62C19A-HS105DKR