参数资料
型号: A3968SLBTR
厂商: Allegro Microsystems Inc
文件页数: 6/8页
文件大小: 0K
描述: IC MOTOR DRIVER PWM DUAL 16SOIC
标准包装: 1,000
应用: PWM 电机驱动器
输出数: 2
电流 - 输出: ±650mA
电压 - 负载: 4.75 V ~ 30 V
电源电压: 4.75 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
A3968
Dual Full-Bridge PWM Motor Driver with Brake
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3968 dual
full-bridges bidirectionally control two DC motors. A n
internal ? xed-frequency PWM control circuit controls the
the load current in each motor. The current-control circuitry
works as follows: when the outputs of the full-bridge are
turned on, current increases in the motor winding. The load
current is sensed by the current-control comparator via
an external sense resistor. R S . Load current continues to
increase until it reaches the predetermined value, set by the
selection of external current-sensing resistors and reference
input voltage (V REF ) according to the equation:
I TRIP = I OUT + I SO = V REF /(4 R S )
where I SO is the sense-current error (typically 18 mA) due
to the base-drive current of the sink driver transistor.
At the trip point, the comparator resets the source-en-
able latch, turning off the source driver of that full-bridge.
The source turn-off of one full-bridge is independent of
the other full-bridge. Load inductance causes the current to
recirculate through the sink driver and ground-clamp diode.
The current decreases until the internal clock oscillator sets
the source-enable latches of both Full-bridges, turning on
the source drivers of both bridges. Load current increases
again, and the cycle is repeated.
The frequency of the internal clock oscillator is set by
the external timing components R T C T . The frequency can
V PHASE
See Enlargement A
be approximately calculated as:
f osc = 1/(R T C T + t blank )
where t blank is de ? ned below.
The range of recommended values for R T and C T are
20 to 100 k ? and 470 to 1000 pF respectively. Nominal
values of 56 k ? and 680 pF result in a clock frequency of
25.4 kHz.
Current-Sense Comparator Blanking. When the
source driver is turned on, a current spike occurs due to the
reverse-recovery currents of the clamp diodes and switch-
ing transients related to distributed capacitance in the load.
To prevent this current spike from erroneously resetting the
source enable latch, the current-control comparator output
is blanked for a short period of time when the source driver
is turned on. The blanking time is set by the timing compo-
nent C T according to the equation:
t blank = 1900 C T ( μ s).
A nominal C T value of 680 pF will give a blanking time
of 1.3 μ s.
The current-control comparator is also blanked when
the load current changes polarity (direction or phase
change). This internally generated blank time is approxi-
mately 1.8 μ s.
V
BB
+
BRIDGE
ON
BRIDGE ON
I
OUT
0
ALL
OFF
SOURCE OFF
ALL OFF
BRIDGE
Enlargement A
ON
I TRIP
SOURCE
OFF
t d
t
blank
RS
INTERNAL
OSCILLATOR
R T C T
Dwg. WM-003-2
Dwg. EP-006-16
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
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