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| 型号： | A3979SLPTR |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/15页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 28-TSSOP |
| 标准包装： | 4,000 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±2.5A |
| 电压 - 负载： | 8 V ~ 35 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 28-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
A3979
DMOS Microstepping Driver with Translator
Fixed Off-Time. The internal PWM current-control cir-
cuitry uses a one-shot timer to control the duration of time
that the MOSFETs remain off. The one shot off-time, t OFF ,
is determined by the selection of external resistors, R T x , and
capacitors, C T x , connected from each R C x timing terminal to
ground. The off-time, over a range of values of C T = 470 pF
to 1500 pF and R T = 12 k Ω to 100 k Ω is approximated by:
t OFF = R T C T
RC Blanking. In addition to the fixed off-time of the
PWM control circuit, the CTx component sets the compara-
tor blanking time. This function blanks the output of the
current-sense comparators when the outputs are switched
by the internal current-control circuitry. The comparator
outputs are blanked to prevent false overcurrent detection
due to reverse recovery currents of the clamp diodes, or to
switching transients related to the capacitance of the load.
The blank time t BLANK can be approximated by:
t BLANK = 1400C T
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB for
driving the source-side DMOS gates. A 0.22 μ F ceramic
capacitor should be connected between CP1 and CP2 for
pumping purposes. In addition, a 0.22 μ F ceramic capacitor
is required between VCP and VBB, to act as a reservoir for
operating the high-side DMOS gates.
V REG (VREG) . This internally-generated voltage is used to
operate the sink-side DMOS outputs. The VREG pin must
be decoupled with a 0.22 μ F capacitor to ground. V REG is
internally monitored, and in the case of a fault condition, the
DMOS outputs of the device are disabled.
Enable Input ( ˉEˉ ˉNˉ ˉAˉ ˉBˉ ˉLˉ ˉEˉ ) . This active-low input
enables all of the DMOS outputs. When set to a logic high,
the outputs are disabled. The inputs to the translator (STEP,
DIR, MS1, and MS2), all remain active, independent of the
ˉEˉ ˉNˉ ˉAˉ ˉBˉ ˉLˉ Eˉ input state.
Shutdown. During normal operation, in the event of a
fault, such as overtemperature (excess T J ) or an undervolt-
age on VCP, the outputs of the device are disabled until the
fault condition is removed.
At power up, and in the event of low V DD , the undervoltage
lockout (UVLO) circuit disables the drivers and resets the
translator to the Home state.
Sleep Mode ( ˉSˉ ˉLˉ ˉEˉ ˉEˉ ˉPˉ ). This active-low control input
is used to minimize power consumption when the motor is
not in use. It disables much of the internal circuitry includ-
ing the output DMOS FETs, current regulator, and charge
pump. Setting this to a logic high allows normal operation,
as well as start-up (at which time the A3979 drives the
motor to the Home microstep position). When bringing the
device out of Sleep mode, in order to allow the charge pump
(gate drive) to stabilize, provide a delay of 1 ms before issu-
ing a step command signal on the STEP input.
Percent Fast Decay Input (PFD). When a STEP
input signal commands a lower output current than the
previous step, it switches the output current decay to either
Slow, Fast, or Mixed decay mode, depending on the voltage
level at the PFD input. If the voltage at the PFD input is
greater than 0.6 × V DD , then Slow decay mode is selected.
If the voltage on the PFD input is less than 0.21 × V DD , then
Fast decay mode is selected. Mixed decay mode is selected
when V PFD is between these two levels, as described in
the next section. This terminal should be decoupled with a
0.1 μ F capacitor.
Mixed Decay Operation. If the voltage on the PFD input
is between 0.6 × V DD and 0.21 × V DD , the bridge operates
in Mixed decay mode, as determined by the step sequence
(shown in figures 2 through 5). As the trip point is reached,
the device goes into Fast decay mode until the voltage
on the RCx terminal decays to the same level as voltage
applied to the PFD terminal. The time that the device oper-
ates in fast decay is approximated by:
t FD = R T C T ln (0.6V DD /V PFD )
After this Fast decay portion, the device switches to Slow
decay mode for the remainder of the fixed off-time period.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
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| A3979SLPTR-T | 功能描述:IC DRIVER MICROSTEPPING 28-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 电机和风扇控制器，驱动器 系列:- 标准包装:1 系列:- 应用:步进电机驱动器，1-2 相，2 相 评估套件:- 输出数:1 电流 - 输出:800mA 电压 - 负载:10 V ~ 28 V 电源电压:4.75 V ~ 5.25 V 工作温度:-20°C ~ 90°C 安装类型:表面贴装 封装/外壳:28-SOP + 2 翼片裸露焊盘 供应商设备封装:28-HSOPHC（15.2x7.9） 包装:剪切带 (CT) 其它名称:869-1268-1 |
| A397A | 制造商:n/a 功能描述:Power Semiconductor |
| A397B | 制造商:Powerex Power Semiconductors 功能描述:DIODE FAST REC 200V 400A |
| A397C | 制造商:n/a 功能描述:Power Semiconductor |
| A397D | 制造商:n/a 功能描述:Power Semiconductor 制造商:Powerex Power Semiconductors 功能描述:DIODE FAST REC 400V 400A |
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