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参数资料
| 型号： | A3984SLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 24-TSSOP |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±2A |
| 电压 - 负载： | 8 V ~ 35 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1150-6 |
A3984
DMOS Microstepping Driver with Translator
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current
control circuitry. The comparator outputs are blanked to prevent
pin is tied to an external voltage > 3 V, then t OFF defaults to 30 μ s. are disabled until the fault condition is removed. At power-on, the
The ROSC pin can be safely connected to the VDD pin for this UVLO (undervoltage lockout) circuit disables the DMOS outputs
purpose. The value of t OFF ( μ s) is approximately and resets the translator to the Home state.
t OFF = R OSC ? 825
Sleep Mode (SLEEP). To minimize power consumption when
the motor is not in use, this input disables much of the internal
circuitry including the output DMOS FETs, current regulator,
false overcurrent detection due to reverse recovery currents of the and charge pump. A logic low on the SLEEP pin puts the A3984
clamp diodes, and switching transients related to the capacitance of into Sleep mode. A logic high allows normal operation, as well as
the load. The blank time, t BLANK ( μ s), is approximately
t BLANK ≈ 1 μ s
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side DMOS gates. A 0.1 μ F ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μ F ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side DMOS gates.
VREG (VREG) . This internally-generated voltage is used to
operate the sink-side DMOS outputs. The VREG pin must be
decoupled with a 0.22 μ F capacitor to ground. VREG is internally
monitored. In the case of a fault condition, the DMOS outputs of
the A3984 are disabled.
start-up (at which time the A3984 drives the motor to the Home
microstep position). When emerging from Sleep mode, in order to
allow the charge pump to stabilize, provide a delay of 1 ms before
issuing a Step command.
Mixed Decay Operation. The bridge can operate in Mixed
Decay mode, depending on the step sequence, as shown in figures
3 thru 5. As the trip point is reached, the A3984 initially goes into
a fast decay mode for 31.25% of the off-time. t OFF . After that, it
switches to Slow Decay mode for the remainder of t OFF .
Synchronous Rectification . When a PWM-off cycle is
triggered by an internal fixed–off-time cycle, load current recir-
Enable Input (ENABLE) . This input turns on or off all of the
DMOS outputs. When set to a logic high, the outputs are disabled.
culates according to the decay mode selected by the control logic.
This synchronous rectification feature turns on the appropriate
When set to a logic low, the internal control enables the outputs as FETs during current decay, and effectively shorts out the body
required. The translator inputs STEP, DIR, MS1, and MS2, as well diodes with the low DMOS R DSON . This reduces power dissipa-
as the internal sequencing logic, all remain active, independent of tion significantly, and can eliminate the need for external Schottky
the ENABLE input state.
diodes in many applications. Turning off synchronous rectification
Shutdown. In the event of a fault, overtemperature (excess T J ) prevents the reversal of the load current when a zero-current level is
or an undervoltage (on VCP), the DMOS outputs of the A3984 detected.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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