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| 型号： | A3988SEVTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRVR PWM QUAD 36-QFN |
| 标准包装： | 1 |
| 应用： | 直流电机驱动器，步进电机驱动器 |
| 输出数： | 2 或 4 |
| 电流 - 输出： | ±1.2A |
| 电压 - 负载： | 8 V ~ 36 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN-EP（6x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1176-6 |
A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Description
Device Operation The A3988 is designed to operate two
stepper motors, four DC motors, or one stepper and two DC
motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse width
modulated (PWM) control circuitry. Each full-bridge peak current
is set by the value of an external current sense resistor, R Sx , and a
reference voltage, V REFx .
If the logic inputs are pulled up to V DD , it is good practice to use
a high value pull-up resistor in order to limit current to the logic
inputs, should an overvoltage event occur. Logic inputs include:
PHASEx, I0x, and I1x.
Internal PWM Current Control Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, I TRIP . Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and R Sx . When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
R S and the voltage at the VREF input with a transconductance
function approximated by:
I TripMax = V REF / (3×R S )
Each current step is a percentage of the maximum current,
I TripMax . The actual current at each step I Trip is approximated by:
I Trip = (% I TripMax / 100) I TripMax
where % I TripMax is given in the Step Sequencing table.
Note: It is critical to ensure that the maximum rating of ? 500 mV
on each SENSEx pin is not exceeded.
Fixed Off-Time The internal PWM current control circuitry
uses a one shot circuit to control the time the drivers remain off.
The one shot off-time, t off , is internally set to 30 μ s.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, t BLANK , is
approximately 1 ? s.
Control Logic Communication is implemented via the indus-
try standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent V REF input so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREF x pins.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than the V BB in order to drive the
source-side DMOS gates. A 0.1 ? F ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes. A 0.1 ? F
ceramic capacitor is required between VCP and VBBx to act as a
reservoir to operate the high-side DMOS devices.
Shutdown In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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